 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| this is information on a product in full production. september 2012 doc id 15081 rev 7 1/98 1 stm32f100xc stm32f100xd stm32f100xe high-density value line, advanc ed arm-based 32-bit mcu with 256 to 512 kb flash, 16 timers , adc, dac & 11 comm interfaces datasheet ? production data features core: arm 32-bit cortex?-m3 cpu ? 24 mhz maximum frequency, 1.25 dmips /mhz (dhrystone 2.1) performance ? single-cycle multiplication and hardware division memories ? 256 to 512 kbytes of flash memory ? 24 to 32 kbytes of sram ? flexible static memory controller with 4 chip selects. supports sram, psram and nor memories ? lcd parallel interface, 8080/6800 modes clock, reset and supply management ? 2.0 to 3.6 v application supply and i/os ? por, pdr and programmable voltage detector (pvd) ? 4-to-24 mhz crystal oscillator ? internal 8 mhz factory-trimmed rc ? internal 40 khz rc ? pll for cpu clock ? 32 khz oscillator for rtc with calibration low power ? sleep, stop and standby modes ?v bat supply for rtc and backup registers serial wire debug (swd) and jtag i/f dma ? 12-channel dma controller ? peripherals supported: timers, adc, spis, i 2 cs, usarts and dacs 1 12-bit, 1.2 s a/d converter (up to 16 ch.) ? conversion range: 0 to 3.6 v ? temperature sensor 2 12-bit d/a converters up to 112 fast i/o ports ? 51/80/112 i/os, all mappable on 16 external interrupt vectors and almost all 5 v-tolerant up to 16 timers ? up to seven 16-bit timers, each with up to 4 ic/oc/pwm or pulse counter ? one 16-bit, 6-channel advanced-control timer: up to 6 channels for pwm output, dead time generation and emergency stop ? one 16-bit timer, with 2 ic/oc, 1 ocn/pwm, dead-time generation and emergency stop ? two 16-bit timers, each with ic/oc/ocn/pwm, dead-time generation and emergency stop ? two watchdog timers ? systick timer: 24-bit downcounter ? two 16-bit basic timers to drive the dac up to 11 communications interfaces ? up to two i 2 c interfaces (smbus/pmbus) ? up to 3 usarts (iso 7816 interface, lin, irda capability, modem control) ? up to 2 uarts ? up to 3 spis (12 mbit/s) ? consumer electronics control (cec) i/f crc calculation unit, 96-bit unique id table 1. device summary reference part number stm32f100xc stm32f100rc, stm32f100vc, stm32f100zc stm32f100xd stm32f100rd, stm32f100vd, stm32f100zd stm32f100xe stm32f100re, stm32f100ve, stm32f100ze lqfp144 20 20 mm lqfp100 14 14 mm lqfp64 10 10 mm www.st.com
contents stm32f100xc, stm32f100xd, stm32f100xe 2/98 doc id 15081 rev 7 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.1 arm? cortex?-m3 core with embedded flash and sram . . . . . . . . . 13 2.2.2 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.3 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 13 2.2.4 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.5 fsmc (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.6 lcd parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.7 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 14 2.2.8 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.9 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.10 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.11 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.12 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.13 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.14 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.15 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.16 rtc (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 16 2.2.17 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.18 i 2 c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.19 universal synchronous/asynchronous receiver transmitter (usart) . . 19 2.2.20 universal asynchronous receiver transmitter (uart) . . . . . . . . . . . . . . 19 2.2.21 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.22 gpios (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.23 remap capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.24 adc (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.25 dac (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.26 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.27 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 stm32f100xc, stm32f100xd, stm32f100xe contents doc id 15081 rev 7 3/98 4 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.3.2 operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 38 5.3.3 embedded reset and power control block characteristics . . . . . . . . . . . 39 5.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3.6 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3.7 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.3.8 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3.9 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3.10 fsmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.3.12 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 67 5.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.3.16 timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.3.17 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.3.18 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.3.19 dac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.3.20 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 contents stm32f100xc, stm32f100xd, stm32f100xe 4/98 doc id 15081 rev 7 6.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.2.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 93 7 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 stm32f100xc, stm32f100xd, stm32f100xe list of tables doc id 15081 rev 7 5/98 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f100xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. high-density stm32f100xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 5. fsmc pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 6. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 7. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 8. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 9. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 10. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 11. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 12. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0 table 13. maximum current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 14. maximum current consumption in run mode, code with data processing running from ram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 15. stm32f100xxb maximum current consumption in sleep mode, code running from flash or ram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 16. typical and maximum current consumptions in stop and standby modes . . . . . . . . . . . . 43 table 17. typical current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 18. typical current consumption in sleep mode, code running from flash or ram . . . . . . . . . 45 table 19. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 20. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 21. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 22. hse 4-24 mhz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 table 23. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 24. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 25. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 26. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 27. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 28. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 29. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 30. asynchronous non-multiplexed sram/psram/nor read timings . . . . . . . . . . . . . . . . . . 56 table 31. asynchronous non-multiplexed sram/psram/nor write timings . . . . . . . . . . . . . . . . . . 57 table 32. asynchronous multiplexed psram/nor read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 33. asynchronous multiplexed psram/nor write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 34. synchronous multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 35. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 36. synchronous non-multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 37. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 38. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 39. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 40. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 41. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 42. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 43. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 44. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 list of tables stm32f100xc, stm32f100xd, stm32f100xe 6/98 doc id 15081 rev 7 table 45. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 46. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 47. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 48. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 49. scl frequency (f pclk1 = 24 mhz, v dd = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 50. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 51. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 52. r ain max for f adc = 12 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 53. adc accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 54. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 55. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 56. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 57. lqfp144, 20 x 20 mm, 144-pin thin quad flat package mechanical data . . . . . . . . . . . . . 89 table 58. lqpf100 ? 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 90 table 59. lqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package mechanical data . . . . . . . . . 91 table 60. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 61. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 62. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 stm32f100xc, stm32f100xd, stm32f100xe list of figures doc id 15081 rev 7 7/98 list of figures figure 1. stm32f100xx value line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3. stm32f100xx value line lqfp144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 4. stm32f100xx value line lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 5. stm32f100xx value line in lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 6. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 7. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 8. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 9. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 10. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 11. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 12. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 13. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 14. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 15. asynchronous non-multiplexed sram/psram/nor read waveforms . . . . . . . . . . . . . . . 55 figure 16. asynchronous non-multiplexed sram/psram/nor write waveforms . . . . . . . . . . . . . . . 57 figure 17. asynchronous multiplexed psram/nor read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 18. asynchronous multiplexed psram/nor write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 19. synchronous multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 20. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 21. synchronous non-multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 22. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 23. standard i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 24. standard i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 0 figure 25. 5 v tolerant i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 26. 5 v tolerant i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 27. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 28. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 29. i 2 c bus ac waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 30. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 31. spi timing diagram - slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 32. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 33. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 34. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 35. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . . 84 figure 36. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . . 84 figure 37. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 38. lqfp144, 20 x 20 mm, 144-pin thin quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 39. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 40. lqfp100 ? 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 90 figure 41. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 42. lqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 91 figure 43. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 44. lqfp100 p d max vs. t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 introduction stm32f100xc, stm32f100xd, stm32f100xe 8/98 doc id 15081 rev 7 1 introduction this datasheet provides the ordering information and mechanical device characteristics of the stm32f100xc, stm32f100xd and stm32f100xe value line microcontrollers. in the rest of the document, the stm32f100xc, stm32f100xd and stm32f100xe are referred to as high-density value line devices. this stm32f100xc, stm32f100xd and stm32f100xe datasheet should be read in conjunction with the stm32f100xx high-density arm-based 32-bit mcus reference manual (rm0059) . for information on programming, erasing and protection of the internal flash memory please refer to the stm32f100xx high-density value line flash programming manual (pm0072). the reference and flash programming manuals are both available from the stmicroelectronics website www.st.com . for information on the cortex?-m3 core please refer to the cortex?-m3 technical reference manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/. stm32f100xc, stm32f100xd, stm32f100xe description doc id 15081 rev 7 9/98 2 description the stm32f100xx value line family incorporates the high-performance arm cortex?-m3 32-bit risc core operating at a 24 mhz frequency, high-speed embedded memories (flash memory up to 512 kbytes and sram up to 32 kbytes), a flexible static memory control (fsmc) interface (for devices offered in packages of 100 pins and more) and an extensive range of enhanced pe ripherals and i/os connected to two apb buses. all devices offer standard communication interfaces (up to two i 2 cs, three spis, one hdmi cec, up to three usarts and 2 uarts), one 12-bit adc, two 12-bit dacs, up to 9 general-purpose 16-bit timers and an advanced-control pwm timer. the stm32f100xx high-density value line family operates in the ?40 to +85 c and ?40 to +105 c temperature ranges, from a 2.0 to 3.6 v power supply. a comprehensive set of power-saving mode allows the design of low-power applications. the stm32f100xx value line family includes devices in three different packages ranging from 64 pins to 144 pins. depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. these features make the stm32f100xx value line microcontroller family suitable for a wide range of applications such as motor drives, application control, medical and handheld equipment, pc and gaming peripherals, gps platforms, industrial applications, plcs, inverters, printers, scanners, alarm systems, video intercoms, and hvacs. description stm32f100xc, stm32f100xd, stm32f100xe 10/98 doc id 15081 rev 7 2.1 device overview table 2. stm32f100xx features and peripheral counts peripheral stm32f100rx stm32f100vx stm32f100zx flash - kbytes 256 384 512 256 384 512 256 384 512 sram - kbytes 24 32 32 24 32 32 24 32 32 fsmc no yes (1) ye s timers advanced-control 111 general-purpose 10 10 10 communication interfaces spi 333 i 2 c 222 usart 333 uart 222 cec 111 12-bit synchronized adc number of channels 1 16 channels 1 16 channels 1 16 channels gpios 51 80 112 12-bit dac number of channels 2 2 2 2 2 2 cpu frequency 24 mhz operating voltage 2.0 to 3.6 v operating temperatures ambient operating temperature: ?40 to +85 c /?40 to +105 c junction temperature: ?40 to +125 c packages lqfp64 lqfp100 lqfp144 1. for the lqfp100 package, only fsmc bank1 is available. bank1 can only support a multiplexed nor/psram memory. stm32f100xc, stm32f100xd, stm32f100xe description doc id 15081 rev 7 11/98 figure 1. stm32f100xx value line block diagram 1. af = alternate function on i/o port pin. 2. t a = ?40 c to +85 c (junction temperature up to 105 c) or t a = ?40 c to +105 c (junction temperature up to 125 c). pa[15:0] ext.i t wwdg 12- b it adc1 16 adc ch a nnel s (adc_inx) jtdi jtck/ s wclk jtm s / s wdio njtr s t jtdo nr s t v dd = 2.0 v to 3 .6 v 8 0 af pb[15:0] pc[15:0] ahb2 wkup gpio port a gpio port b gpio port c f m a x : 24 mhz v ss v ref+ gp dma tim2 tim 3 xtal o s c 4-24 mhz xtal 3 2 khz o s c_in o s c_out o s c 3 2_out o s c 3 2_in apb1: f m a x = 24 mhz hclk pclk1 fl as h 512 kb volt a ge reg. 3 . 3 v to 1. 8 v v dd1 8 power b a ck u p interf a ce as af tim4 3 2 b it rtc awu rc h s cortex-m 3 cpu i bus d bus o b l u s art1 u s art2 s pi2 12 ch a nnel s b a ck u p regi s ter tim15 i2c1 rx,tx, ct s , rt s , u s art 3 temp s en s or pd[15:0] gpio port d pe[15:0] gpio port e fclk rc l s s t a nd b y iwdg @vdd 33 @v bat por / pdr su pply su pervi s ion @vdda vdda v ss a @vdda v ba t = 1. 8 v to 3 .6 v . ck as af rx, tx, ct s , rt s , ck as af rx,tx, ct s , rt s , ck as af s pi1 if interf a ce @vdda pvd re s et int @vdd ahb2 apb 2 apb1 por tam per-rtc s y s tem tim16 re s et & clock control pclk2 pll 12- b it dac1 if 12- b it dac2 @vdda dac1_out as af dac2 _out as af s ram 3 2 kb tim6 tim7 (alarm out) nvic traceclk traced[0: 3 ] as af tim17 jtag & s w p bus tr a ce controller ahb : f m a x = i2c2 hdmi cec hdmi cec as af 4 ch a nnel s as af 4 ch a nnel s as af 4 ch a nnel s as af mo s i, mi s o, s ck, n ss as af mo s i, mi s o, s ck, n ss as af v ref? 2 ch a nnel s , 1 compl. ch a nnel a nd bkin as af fl as h interf a ce b us m a trix s cl, s da, s mba as af s cl, s da, s mba as af a i17515 b tim1 4 ch a nnel s , 3 compl. ch a nnel s , etr a nd bkin as af 24 mhz 1 ch a nnel, 1 compl. ch a nnel a nd bkin as af 1 ch a nnel, 1 compl. ch a nnel a nd bkin as af tim12 tim1 3 tim14 2 ch a nnel s as af 1 ch a nnel as af 1 ch a nnel as af tim5 4 ch a nnel s uart4 rx,tx, ct s , rt s , ck as af uart5 rx,tx, ct s , r ck as af s pi 3 mo s i, mi s o, s ck, n ss as af apb2: f m a x = 24 mhz f s mc a[25:0] d[15:0] clk noe nwe ne[ 3 :0] nbl[1:0] nwait nadv as af gpio port f gpio port g pf[15:0] pg[15:0] description stm32f100xc, stm32f100xd, stm32f100xe 12/98 doc id 15081 rev 7 figure 2. clock tree 1. to obtain an adc conversion time of 1.2 s, apb2 must be at 24 mhz. ! "#$% &'()*+ , - .-.- , / &% 0! - 1 #2$2 $0 & #2 / " 0! - 1 #2$2 $0 & #2 / " 0! 1 #2$2 $0 & #2 / &% 0! 1 #2$2 $0 & #2 & 3 $2 $ 4 !4 # .-5 67 ,1 0$#2 1 85. 95 8 ,: 6,75 ,1 0$#2 1 85. ...5 6) ,1 0$#2 1 8 ... 6):5 ;#- ,:5 : ,: 67<40.$ 1 . ; ; 1=# ) 6 6)5 85 8 ! 1 !% 1#20 6,75 , 1 !% 1#22 $ #<2 #<2 , 1 !% 1#22 $ 6,7 ,1 0$#2 1 85. ...5 ,: 58598585 ; 10 5. 59. 5# 5 ! 1 !% 1#20 6,7 , 1 !% 1#22 $ #<2 #<2 , 1 !% 1#22 $ ;#- ;#- ;#- , ( 1 -=0 ; ; 1 8 2 $ #<2 >: ;#- : ?53@ -: -: ()*: >: a: 1 - b1 14 &$2 $ # 5 b'6,75!1 0$#2 1/5+-5 20 - b'6,7 !1 0$#2 1/5+-5 20 - ,)c5 858 88 85985 #<2 a : a , 1 !% 1#2$2 $ ...9...5 .5.5 ...9...5 .5.5 a2#0%!1 &1#;; & 1b#$ aa: stm32f100xc, stm32f100xd, stm32f100xe description doc id 15081 rev 7 13/98 2.2 overview 2.2.1 arm ? cortex?-m3 core with embedded flash and sram the arm cortex?-m3 processor is the latest generation of arm processors for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm cortex?-m3 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the stm32f100xx value line family having an embedded arm core, is therefore compatible with all arm tools and software. 2.2.2 embedded flash memory up to 512 kbytes of embedded flash memory is available for storing programs and data. 2.2.3 crc (cyclic redundanc y check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc ca lculation unit helps co mpute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 2.2.4 embedded sram up to 32 kbytes of embedded sram accessed (read/write) at cpu clock speed with 0 wait states. 2.2.5 fsmc (flexible static memory controller) the fsmc is embedded in the high-density value line family. it has four chip select outputs supporting the following mo des: sram, psram, and nor. functionality overview: the three fsmc interrupt lines are ored in order to be connected to the nvic no read fifo code execution from external memory no boot capability the targeted frequency is hclk/2, so external access is at 12 mhz when hclk is at 24 mhz 2.2.6 lcd parallel interface the fsmc can be configured to interface seamlessly with most graphic lcd controllers. it supports the intel 8080 and motorola 6800 modes, and is flexible enough to adapt to description stm32f100xc, stm32f100xd, stm32f100xe 14/98 doc id 15081 rev 7 specific lcd interfaces. this lcd parallel interface capability makes it easy to build cost- effective graphic applications using lcd modules with embedded controllers or high- performance solutions using external controllers with dedicated acceleration. 2.2.7 nested vectored interrupt controller (nvic) the stm32f100xx value line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of cortex?-m3) and 16 priority levels. closely coupled nvic gives low latency interrupt processing interrupt entry vector table address passed directly to the core closely coupled nvic core interface allows early processing of interrupts processing of late arriving higher priority interrupts support for tail-chaining processor state automatically saved interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimal interrupt latency. 2.2.8 external interrupt /event controller (exti) the external interrupt/event controller consists of 18 edge detector lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal apb2 cloc k period. up to 112 gp ios can be connected to the 16 external interrupt lines. 2.2.9 clocks and startup system clock selection is performed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an ex ternal 4-24 mhz clock can be selected, in which case it is monitored for failure. if failure is detected, the system automatically switches back to the internal rc oscillato r. a software interrupt is genera ted if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example on failure of an indirectly used extern al crystal, resonator or oscillator). several prescalers allow the configuration of the ahb frequency, the high-speed apb (apb2) and the low-speed apb (apb1) domains. the maximum freque ncy of the ahb and the apb domains is 24 mhz. 2.2.10 boot modes at startup, boot pins are used to select one of three boot options: boot from user flash boot from system memory boot from embedded sram stm32f100xc, stm32f100xd, stm32f100xe description doc id 15081 rev 7 15/98 the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1. for further details please refer to an2606. 2.2.11 power supply schemes v dd = 2.0 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through v dd pins. v ssa , v dda = 2.0 to 3.6 v: external analog power supplies for adc, dac, reset blocks, rcs and pll (minimum voltage to be applied to v dda is 2.4 v when the adc or dac is used). v dda and v ssa must be connected to v dd and v ss , respectively. v bat = 1.8 to 3.6 v: power supply for rtc, ex ternal clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. 2.2.12 power supply supervisor the device has an integrated power on reset (por)/power down reset (pdr) circuitry. it is always active, and ensures proper operation starting from/down to 2 v. the device remains in reset mode when v dd is below a specified threshold, v por/pdr , without the need for an external reset circuit. the device features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 2.2.13 voltage regulator the regulator has three operation modes: main (mr), low power (lpr) and power down. mr is used in the nominal regulation mode (run) lpr is used in the stop mode power down is used in standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing ze ro consumption (but the contents of the registers and sram are lost) this regulator is always enabled after reset. it is disabled in standby mode, providing high impedance output. 2.2.14 low-power modes the stm32f100xx value line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. stop mode stop mode achieves the lowest power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled. the voltage regulator can also be put description stm32f100xc, stm32f100xd, stm32f100xe 16/98 doc id 15081 rev 7 either in normal or in low power mode. the device can be woken up from stop mode by any of the exti line. the exti line source can be one of the 16 external lines, the pvd output or the rtc alarm. standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillators are also switched off. after entering standby mode, sram and register contents are lost except for registers in the backup domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), a iwdg reset, a rising edge on the wkup pin, or an rtc alarm occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode. 2.2.15 dma the flexible 12-channel general-purpose dma is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the two dma controllers support circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. each channel is connected to dedicated hardware dma requests, with support for software trigger on each channel. configuration is made by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, dac, i 2 c, usart, all timers and adc. 2.2.16 rtc (real-time cl ock) and backup registers the rtc and the backup registers are supplied through a switch that takes power either on v dd supply when present or through the v bat pin. the backup registers are ten 16-bit registers used to store 20 bytes of user application data when v dd power is not present. the real-time clock provides a set of continuo usly running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. it is clocke d by a 32.768 khz external crysta l, resonator or oscillator, the internal low power rc oscillator or the high -speed external clock divided by 128. the internal low power rc has a typical frequency of 40 khz. the rtc can be calibrated using an external 512 hz output to compensate for any natural crystal deviation. the rtc features a 32-bit programmable counter for long term measurement using the compare register to generate an alarm. a 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 khz. 2.2.17 timers and watchdogs the stm32f100xx devices include an advanced-control timer, nine general-purpose timers, two basic timers and two watchdog timers. ta bl e 3 compares the features of the advanced-control, general-purpose and basic timers. stm32f100xc, stm32f100xd, stm32f100xe description doc id 15081 rev 7 17/98 advanced-control timer (tim1) the advanced-control timer (tim1) can be seen as a three-phase pwm multiplexed on 6 channels. it has complementary pwm outputs with programmable inserted dead times. it can also be seen as a complete general-purpose timer. the 4 independent channels can be used for: input capture output compare pwm generation (edge or center-aligned modes) one-pulse mode output if configured as a standard 16-bit timer, it has the same features as the timx timer. if configured as the 16-bit pw m generator, it has full modu lation capability (0-100%). the counter can be frozen in debug mode. many features are shared with those of the standard tim timers which have the same architecture. the advanced control timer can th erefore work together with the tim timers via the timer link feature for synchronization or event chaining. general-purpose timers (tim2..5, tim12..17) there are ten synchronizable general-purpose timers embedded in the stm32f100xx devices (see ta bl e 3 for differences). each general-purpose timer can be used to generate pwm outputs, or as simple time base. table 3. timer feature comparison timer counter resolution counter type prescaler factor dma request generation capture/compare channels complementary outputs tim1 16-bit up, down, up/down 16 bits yes 4 yes tim2, tim3, tim4, tim5 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 n o tim12 16-bit up any integer between 1 and 65536 no 2 no tim13, tim14 16-bit up any integer between 1 and 65536 no 1 no tim15 16-bit up any integer between 1 and 65536 ye s 2 ye s tim16, tim17 16-bit up any integer between 1 and 65536 ye s 1 ye s tim6, tim7 16-bit up any integer between 1 and 65536 ye s 0 n o description stm32f100xc, stm32f100xd, stm32f100xe 18/98 doc id 15081 rev 7 tim2, tim3, tim4, tim5 stm32f100xx devices feature four synchron izable 4-channel general-purpose timers. these timers are based on a 16-bit auto-rel oad up/downcounter and a 16-bit prescaler. they feature 4 independent channels each for input capture/output compare, pwm or one- pulse mode output. this gives up to 12 input captures/output compares/pwms on the largest packages. the tim2, tim3, tim4, tim5 general-purpose timers can work together or with the tim1 advanced-control timer via the timer link fe ature for synchronization or event chaining. tim2, tim3, tim4, tim5 all have independent dma request generation. these timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. their counters can be frozen in debug mode. tim12, tim13 and tim14 these timers are based on a 16-bit auto-r eload upcounter and a 16-bit prescaler. tim12 has two independent channels, whereas tim13 and tim14 feature one single channel for input capture/output compare, pwm or one-pulse mode output. their counters can be frozen in debug mode. tim15, tim16 and tim17 these timers are based on a 16-bit auto-r eload upcounter and a 16-bit prescaler. tim15 has two independent channels, whereas tim16 and tim17 feature one single channel for input capture/output compare, pwm or one-pulse mode output. the tim15, tim16 and tim17 timers can work together, and tim15 can also operate with tim1 via the timer link feature for synchronization or event chaining. tim15 can be synchronized with tim16 and tim17. tim15, tim16, and tim17 have a complementary output with dead-time generation and independent dma request generation their counters can be frozen in debug mode. basic timers tim6 and tim7 these timers are mainly used for dac trigger generation. they can also be used as a generic 16-bit time base. independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. stm32f100xc, stm32f100xd, stm32f100xe description doc id 15081 rev 7 19/98 window watchdog the window watchdog is based on a 7-bit downcoun ter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrup t capability and the counter can be frozen in debug mode. systick timer this timer is dedicated for os, but could al so be used as a standard down counter. it features: a 24-bit down counter autoreload capability maskable system interrupt generation when the counter reaches 0. programmable clock source 2.2.18 i 2 c bus the i2c bus interface can operate in multimaster and slave modes. it can support standard and fast modes. it supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. a hardware crc generation/verification is embedded. the interface can be served by dma and it supports sm bus 2.0/pm bus. 2.2.19 universal sy nchronous/asynchronous receiver transmitter (usart) the stm32f100xx value line embeds three universal synchronous/asynchronous receiver transmitters (usart1, usart2 and usart3). the available usart interfaces communicate at up to 3 mbit/s. they provide hardware management of the cts and rts signals, they support irda sir endec, the multiprocessor communication mode, the single-wire half-duplex communication mode and have lin master/slave capability. the usart interfaces can be served by the dma controller. 2.2.20 universal asynchronous receiver transmitter (uart) the stm32f100xx value line embeds 2 universal asynchronous receiver transmitters (uart4, and uart5). the available uart interfaces support irda sir endec, the multiprocessor communication mode, the single-wire half-duplex communication mode and have lin master/slave capability. the uart interfaces can be served by the dma controller. 2.2.21 serial perip heral interface (spi) up to three spis are able to communicate up to 12 mbit/s in slave and master modes in full- duplex and simplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the spis can be served by the dma controller. description stm32f100xc, stm32f100xd, stm32f100xe 20/98 doc id 15081 rev 7 hdmi (high-definition multimedia interface) consumer electronics control (cec) the stm32f100xx value line embeds a hdmi-cec controller that provides hardware support of consumer electronics control (cec) (appendix supplement 1 to the hdmi standard). this protocol provides high-level control functions between all audiovisual products in an environment. it is specified to operate at low speeds with minimum processing and memory overhead. 2.2.22 gpios (genera l-purpose inputs/outputs) each of the gpio pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high current capable. the i/os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. 2.2.23 remap capability this feature allows the use of a maximum nu mber of peripherals in a given application. indeed, alternate functions are available not only on the default pins but also on other specific pins onto which they are remappable. this has the advantage of making board design and port usage much more flexible. for details refer to table 4: high-density stm32f100xx pin definitions ; it shows the list of remappable alternate functions and the pins onto which they can be remapped. see the stm32f100xx reference manual for software considerations. 2.2.24 adc (analog-to -digital converter) the 12-bit analog to digital converter has up to 16 external channels and performs conversions in single-shot or scan modes. in scan mode, automatic conversion is performed on a selected group of analog inputs. the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. 2.2.25 dac (digital-t o-analog converter) the two 12-bit buffered dac channels can be used to convert two digital signals into two analog voltage signal outputs. the chosen design structure is composed of integrated resistor strings and an amplifier in noninverting configuration. stm32f100xc, stm32f100xd, stm32f100xe description doc id 15081 rev 7 21/98 this dual digital interface supports the following features: two dac converters: one for each output channel up to 10-bit output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual dac channels? independent or simultaneous conversions dma capability for each channel external triggers for conversion input voltage reference v ref+ eight dac trigger inputs are used in the stm32f100xx. the dac channels are triggered through the timer update outputs that are also connected to different dma channels. 2.2.26 temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 2 v < v dda < 3.6 v. the temperature sensor is internally connected to the adc1_in16 input channel which is used to convert the sensor output voltage into a digital value. 2.2.27 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jtag tms and tck pins are shared respectively with swdio and swclk and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. pinouts and pin descriptions stm32f100xc, stm32f100xd, stm32f100xe 22/98 doc id 15081 rev 7 3 pinouts and pin descriptions figure 3. stm32f100xx value line lqfp144 pinout v dd_3 v ss_3 pe1 pe0 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pg15 v dd_11 v ss_11 pg14 pg13 pg12 pg11 pg10 pg9 pd7 pd6 v dd_10 v ss_10 pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc11 pc10 pa15 pa14 pe2 v dd_2 pe3 v ss_2 pe4 nc pe5 pa13 pe6 pa12 vbat pa11 pc13-tamper-rtc pa10 pc14-osc32_in pa9 pc15-osc32_out pa8 pf0 pc9 pf1 pc8 pf2 pc7 pf3 pc6 pf4 v dd_9 pf5 v ss_9 v ss_5 pg8 v dd_5 pg7 pf6 pg6 pf7 pg5 pf8 pg4 pf9 pg3 pf10 pg2 osc_in pd15 osc_out pd14 nrst v dd_8 pc0 v ss_8 pc1 pd13 pc2 pd12 pc3 pd11 v ssa pd10 v ref- pd9 v ref+ pd8 v dda pb15 pa0-wkup pb14 pa1 pb13 pa2 pb12 pa3 v ss_4 v dd_4 pa4 pa5 pa6 pa7 pc4 pc5 pb0 pb1 pb2 pf11 pf12 vss_6 v dd_6 pf13 pf14 pf15 pg0 pg1 pe7 pe8 pe9 v ss_7 v dd_7 pe10 pe11 pe12 pe13 pe14 pe15 pb10 pb11 v ss_1 v dd_1 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 109 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 72 lqfp144 120 119 118 117 116 115 114 113 112 111 110 61 62 63 64 65 66 67 68 69 70 71 26 27 28 29 30 31 32 33 34 35 36 83 82 81 80 79 78 77 76 75 74 73 ai14667 stm32f100xc, stm32f100xd, stm32f100xe pinouts and pin descriptions doc id 15081 rev 7 23/98 figure 4. stm32f100xx value line lqfp100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 vdd_2 vss_2 nc pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pc9 pc8 pc7 pc6 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pb15 pb14 pb13 pb12 pa 3 vss_4 vdd_4 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pe7 pe8 pe9 pe10 pe11 pe12 pe13 pe14 pe15 pb10 pb11 vss_1 vdd_1 vdd_3 vss_3 pe1 pe0 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc11 pc10 pa15 pa14 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 pe2 pe3 pe4 pe5 pe6 vbat pc13-tamper-rtc pc14-osc32_in pc15-osc32_out vss_5 vdd_5 osc_in osc_out nrst pc0 pc1 pc2 pc3 vssa vref- vref+ vdda pa 0 - w k u p pa 1 pa 2 ai14391 lqfp100 pinouts and pin descriptions stm32f100xc, stm32f100xd, stm32f100xe 24/98 doc id 15081 rev 7 figure 5. stm32f100xx value line in lqfp64 pinout table 4. high-density stm32f100xx pin definitions pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lqfp144 lqfp100 lqfp64 default remap 1 1 - pe2 i/o ft pe2 traceck/ fsmc_a23 2 2 - pe3 i/o ft pe3 traced0/fsmc_a19 3 3 - pe4 i/o ft pe4 traced1/fsmc_a20 4 4 - pe5 i/o ft pe5 traced2/fsmc_a21 5 5 - pe6 i/o ft pe6 traced3/fsmc_a22 661 v bat sv bat 772 pc13-tamper- rtc (5) i/o pc13 (6) tamper-rtc 883 pc14- osc32_in (5) i/o pc14 (6) osc32_in 994 pc15- osc32_out (5) i/o pc15 (6) osc32_out 10 - - pf0 i/o ft pf0 fsmc_a0 11 - - pf1 i/o ft pf1 fsmc_a1 12 - - pf2 i/o ft pf2 fsmc_a2 13 - - pf3 i/o ft pf3 fsmc_a3 14 - - pf4 i/o ft pf4 fsmc_a4 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vbat pc13-tamper-rtc pc14-osc32_in pc15-osc32_out pd0 osc_in pd1 osc_out nrst pc0 pc1 pc2 pc3 vssa vdda pa 0 - w k u p pa 1 pa 2 vdd_3 vss_3 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd2 pc12 pc11 pc10 pa 1 5 pa 1 4 vdd_2 vss_2 pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pc9 pc8 pc7 pc6 pb15 pb14 pb13 pb12 pa 3 vss_4 vdd_4 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pb10 pb11 vss_1 vdd_1 lqfp64 ai14392 stm32f100xc, stm32f100xd, stm32f100xe pinouts and pin descriptions doc id 15081 rev 7 25/98 15 - - pf5 i/o ft pf5 fsmc_a5 16 10 - v ss_5 sv ss_5 17 11 - v dd_5 sv dd_5 18 - - pf6 i/o pf6 19 - - pf7 i/o pf7 20 - - pf8 i/o pf8 21 - - pf9 i/o pf9 22 - - pf10 i/o pf10 23 12 5 osc_in i osc_in pd0 (7) 24 13 6 osc_out o osc_out pd1 (7) 25 14 7 nrst i/o nrst 26 15 8 pc0 i/o pc0 adc_in10 27 16 9 pc1 i/o pc1 adc_in11 28 17 10 pc2 i/o pc2 adc_in12 29 18 11 pc3 i/o pc3 adc_in13 30 19 12 v ssa sv ssa 31 20 - v ref- sv ref- 32 21 - v ref+ sv ref+ 33 22 13 v dda sv dda 34 23 14 pa0-wkup i/o pa0 wkup/usart2_cts (8) adc_in0 tim2_ch1_etr tim5_ch1 35 24 15 pa1 i/o pa1 usart2_rts (8) adc_in1/ tim5_ch2/tim2_ch2 (8) 36 25 16 pa2 i/o pa2 usart2_tx (8) /tim5_ch3 adc_in2/ tim15_ch1 tim2_ch3 (8) 37 26 17 pa3 i/o pa3 usart2_rx (8) /tim5_ch4 adc_in3/tim2_ch4 (8) / tim15_ch2 38 27 18 v ss_4 sv ss_4 39 28 19 v dd_4 sv dd_4 table 4. high-density stm32f100xx pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lqfp144 lqfp100 lqfp64 default remap pinouts and pin descriptions stm32f100xc, stm32f100xd, stm32f100xe 26/98 doc id 15081 rev 7 40 29 20 pa4 i/o pa4 spi1_nss (8) / usart2_ck (8) dac_out1/adc_in4 41 30 21 pa5 i/o pa5 spi1_sck (8) dac_out2/adc_in5 42 31 22 pa6 i/o pa6 spi1_miso (8) / adc_in6 / tim3_ch1 (8) tim1_bkin / tim16_ch1 43 32 23 pa7 i/o pa7 spi1_mosi (8) / adc_in7 / tim3_ch2 (8) tim1_ch1n/ tim17_ch1 44 33 24 pc4 i/o pc4 adc_in14 / tim12_ch1 45 34 25 pc5 i/o pc5 adc_in15 / tim12_ch2 46 35 26 pb0 i/o pb0 adc_in8/tim3_ch3 tim1_ch2n / tim13_ch1 47 36 27 pb1 i/o pb1 adc_in9/tim3_ch4 (8) tim1_ch3n / tim14_ch1 48 37 28 pb2 i/o ft pb2/boot1 49 - - pf11 i/o ft pf11 50 - - pf12 i/o ft pf12 fsmc_a6 51 - - v ss_6 sv ss_6 52 - - v dd_6 sv dd_6 53 - - pf13 i/o ft pf13 fsmc_a7 54 - - pf14 i/o ft pf14 fsmc_a8 55 - - pf15 i/o ft pf15 fsmc_a9 56 - - pg0 i/o ft pg0 fsmc_a10 57 - - pg1 i/o ft pg1 fsmc_a11 58 38 - pe7 i/o ft pe7 fsmc_d4 tim1_etr 59 39 - pe8 i/o ft pe8 fsmc_d5 tim1_ch1n 60 40 - pe9 i/o ft pe9 fsmc_d6 tim1_ch1 61 - - v ss_7 sv ss_7 62 - - v dd_7 sv dd_7 63 41 - pe10 i/o ft pe10 fsmc_d7 tim1_ch2n 64 42 - pe11 i/o ft pe11 fsmc_d8 tim1_ch2 65 43 - pe12 i/o ft pe12 fsmc_d9 tim1_ch3n 66 44 - pe13 i/o ft pe13 fsmc_d10 tim1_ch3 table 4. high-density stm32f100xx pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lqfp144 lqfp100 lqfp64 default remap stm32f100xc, stm32f100xd, stm32f100xe pinouts and pin descriptions doc id 15081 rev 7 27/98 67 45 - pe14 i/o ft pe14 fsmc_d11 tim1_ch4 68 46 - pe15 i/o ft pe15 fsmc_d12 tim1_bkin 69 47 29 pb10 i/o ft pb10 i2c2_scl/usart3_tx (8) tim2_ch3 / hdmi_cec 70 48 30 pb11 i/o ft pb11 i2c2_sda/usart3_rx (8) tim2_ch4 71 49 31 v ss_1 sv ss_1 72 50 32 v dd_1 sv dd_1 73 51 33 pb12 i/o ft pb12 spi2_nss/ i2c2_smba/ usart3_ck (8) / tim1_bkin (8) tim12_ch1 74 52 34 pb13 i/o ft pb13 spi2_sck/ usart3_cts (8) / tim1_ch1n tim12_ch2 75 53 35 pb14 i/o ft pb14 spi2_miso/tim1_ch2n usart3_rts (8) / tim15_ch1 76 54 36 pb15 i/o ft pb15 spi2_mosi/ tim1_ch3n (8) / tim15_ch1n tim15_ch2 77 55 - pd8 i/o ft pd8 fsmc_d13 usart3_tx 78 56 - pd9 i/o ft pd9 fsmc_d14 usart3_rx 79 57 - pd10 i/o ft pd10 fsmc_d15 usart3_ck 80 58 - pd11 i/o ft pd11 fsmc_a16 usart3_cts 81 59 - pd12 i/o ft pd12 fsmc_a17 tim4_ch1 / usart3_rts 82 60 - pd13 i/o ft pd13 fsmc_a18 tim4_ch2 83 - - v ss_8 sv ss_8 84 - - v dd_8 sv dd_8 85 61 - pd14 i/o ft pd14 fsmc_d0 tim4_ch3 86 62 - pd15 i/o ft pd15 fsmc_d1 tim4_ch4 87 - - pg2 i/o ft pg2 fsmc_a12 88 - - pg3 i/o ft pg3 fsmc_a13 89 - - pg4 i/o ft pg4 fsmc_a14 90 - - pg5 i/o ft pg5 fsmc_a15 91 - - pg6 i/o ft pg6 92 - - pg7 i/o ft pg7 table 4. high-density stm32f100xx pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lqfp144 lqfp100 lqfp64 default remap pinouts and pin descriptions stm32f100xc, stm32f100xd, stm32f100xe 28/98 doc id 15081 rev 7 93 - - pg8 i/o ft pg8 94 - - v ss_9 sv ss_9 95 - - v dd_9 sv dd_9 96 63 37 pc6 i/o ft pc6 tim3_ch1 97 64 38 pc7 i/o ft pc7 tim3_ch2 98 65 39 pc8 i/o ft pc8 tim13_ch1 tim3_ch3 99 66 40 pc9 i/o ft pc9 tim14_ch1 tim3_ch4 100 67 41 pa8 i/o ft pa8 usart1_ck/ tim1_ch1 (8) /mco 101 68 42 pa9 i/o ft pa9 usart1_tx (8) / tim1_ch2 (8) / tim15_bkin 102 69 43 pa10 i/o ft pa10 usart1_rx (8) / tim1_ch3 (8) / tim17_bkin 103 70 44 pa11 i/o ft pa11 usart1_cts / tim1_ch4 (8) 104 71 45 pa12 i/o ft pa12 usart1_rts / tim1_etr (8) 105 72 46 pa13 i/o ft jtms- swdio 106 73 - not connected 107 74 47 v ss_2 sv ss_2 108 75 48 v dd_2 sv dd_2 109 76 49 pa14 i/o ft jtck- swclk 110 77 50 pa15 i/o ft jtdi spi3_nss tim2_ch1_etr / spi1_nss 111 78 51 pc10 i/o ft pc10 uart4_tx usart3_tx 112 79 52 pc11 i/o ft pc11 uart4_rx usart3_rx 113 80 53 pc12 i/o ft pc12 uart5_tx usart3_ck 114 81 - pd0 i/o ft pd0 fsmc_d2 (9) 115 82 - pd1 i/o ft pd1 fsmc_d3 (9) 116 83 54 pd2 i/o ft pd2 tim3_etr/uart5_rx 117 84 - pd3 i/o ft pd3 fsmc_clk usart2_cts 118 85 - pd4 i/o ft pd4 fsmc_noe usart2_rts table 4. high-density stm32f100xx pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lqfp144 lqfp100 lqfp64 default remap stm32f100xc, stm32f100xd, stm32f100xe pinouts and pin descriptions doc id 15081 rev 7 29/98 119 86 - pd5 i/o ft pd5 fsmc_nwe usart2_tx 120 - - v ss_10 sv ss_10 121 - - v dd_10 sv dd_10 122 87 - pd6 i/o ft pd6 fsmc_nwait usart2_rx 123 88 - pd7 i/o ft pd7 fsmc_ne1 usart2_ck 124 - - pg9 i/o ft pg9 fsmc_ne2 125 - - pg10 i/o ft pg10 fsmc_ne3 126 - - pg11 i/o ft pg11 127 - - pg12 i/o ft pg12 fsmc_ne4 128 - - pg13 i/o ft pg13 fsmc_a24 129 - - pg14 i/o ft pg14 fsmc_a25 130 - - v ss_11 s v ss_11 131 - - v dd_11 s v dd_11 132 - - pg15 i/o ft pg15 133 89 55 pb3/ i/o ft jtdo spi3_sck pb3/traceswo tim2_ch2 / spi1_sck 134 90 56 pb4 i/o ft njtrst spi3_miso tim3_ch1 spi1_miso 135 91 57 pb5 i/o pb5 i2c1_smba/ spi3_mosi tim16_bkin tim3_ch2 / spi1_mosi 136 92 58 pb6 i/o ft pb6 i2c1_scl (8) / tim4_ch1 (8) / tim16_ch1n usart1_tx 137 93 59 pb7 i/o ft pb7 i2c1_sda (8) / fsmc_nadv / tim4_ch2 (8) / tim17_ch1n usart1_rx 138 94 60 boot0 i boot0 139 95 61 pb8 i/o ft pb8 tim4_ch3 (8) /tim16_ch1 / hdmi_cec i2c1_scl 140 96 62 pb9 i/o ft pb9 tim4_ch4 (8) / tim17_ch1 i2c1_sda 141 97 - pe0 i/o ft pe0 tim4_etr / fsmc_nbl0 142 98 - pe1 i/o ft pe1 fsmc_nbl1 143 99 63 v ss_3 sv ss_3 144 100 64 v dd_3 sv dd_3 1. i = input, o = output, s = supply. table 4. high-density stm32f100xx pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lqfp144 lqfp100 lqfp64 default remap pinouts and pin descriptions stm32f100xc, stm32f100xd, stm32f100xe 30/98 doc id 15081 rev 7 2. ft = 5 v tolerant. 3. function availability depends on the chosen device. 4. if several peripherals share the same i/o pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bi t (in the corresponding rcc peripheral clock enable register). 5. pc13, pc14 and pc15 are supplied through the power switch. since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc 15 in output mode is limited: the speed should not exceed 2 mhz with a maximum load of 30 pf and these io s must not be used as a current source (e.g. to drive an led). 6. main function after the first backup domain power- up. later on, it depends on the contents of the backup registers even after reset (because these registers are not reset by the main reset). for details on how to manage these ios, refer to the battery backup domain and bkp register descr iption sections in the stm32f100xx reference manual, available from t he stmicroelectronics w ebsite: www.st.com. 7. for the lqfp64 package, the pins number 5 and 6 are configured as osc_in/osc_out after reset, however the functionality of pd0 and pd1 can be re mapped by software on these pins. for the lqfp100 and lqfp144 packages, pd0 and pd1 are available by default, so there is no need for remapping. for more details, refer to alternate function i/o and debug configuration section in the stm32f100xx reference manual. 8. this alternate function can be remapped by software to some other port pins (if available on the used package). for more details, refer to the alternate function i/o and debug configuration section in the stm32f100xx reference manual, available from t he stmicroelectronics w ebsite: www.st.com. 9. for devices delivered in lqfp64 packages, the fsmc f unction is not available. table 5. fsmc pin definition pins fsmc lqfp100 (1) nor/psram/sram nor/psram mux pe2 a23 a23 yes pe3 a19 a19 yes pe4 a20 a20 yes pe5 a21 a21 yes pe6 a22 a22 yes pf0 a0 - pf1 a1 - pf2 a2 - pf3 a3 - pf4 a4 - pf5 a5 - pf6 - pf7 - pf8 - pf9 - pf10 - pf11 - pf12 a6 - pf13 a7 - stm32f100xc, stm32f100xd, stm32f100xe pinouts and pin descriptions doc id 15081 rev 7 31/98 pf14 a8 - pf15 a9 - pg0 a10 - pg1 a11 - pe7 d4 da4 yes pe8 d5 da5 yes pe9 d6 da6 yes pe10 d7 da7 yes pe11 d8 da8 yes pe12 d9 da9 yes pe13 d10 da10 yes pe14 d11 da11 yes pe15 d12 da12 yes pd8 d13 da13 yes pd9 d14 da14 yes pd10 d15 da15 yes pd11 a16 a16 yes pd12 a17 a17 yes pd13 a18 a18 yes pd14 d0 da0 yes pd15 d1 da1 yes pg2 a12 - pg3 a13 - pg4 a14 - pg5 a15 - pg6 - pg7 - pd0 d2 da2 yes pd1 d3 da3 yes pd3 clk clk yes pd4 noe noe yes pd5 nwe nwe yes pd6 nwait nwait yes table 5. fsmc pin definition (continued) pins fsmc lqfp100 (1) nor/psram/sram nor/psram mux memory mapping stm32f100xc, stm32f100xd, stm32f100xe 32/98 doc id 15081 rev 7 4 memory mapping the memory map is shown in figure 6 . pd7 ne1 ne1 yes pg9 ne2 ne2 - pg10 ne3 ne3 - pg11 - pg12 ne4 ne4 - pg13 a24 a24 - pg14 a25 a25 - pb7 nadv nadv yes pe0 nbl0 nbl0 yes pe1 nbl1 nbl1 yes 1. ports f and g are not available in dev ices delivered in 100-pin packages. table 5. fsmc pin definition (continued) pins fsmc lqfp100 (1) nor/psram/sram nor/psram mux stm32f100xc, stm32f100xd, stm32f100xe doc id 15081 rev 7 33/98 figure 6. memory map apb memory s pace dma1 rtc wwdg iwdg s pi2 u s art2 u s art 3 adc1 u s art1 s pi1 exti rcc 0 1 2 3 4 5 6 7 peripheral s s ram re s erved re s erved option byte s re s erved 0x4000 0000 0x4000 0400 0x4000 0 8 00 0x4000 0c00 0x4000 2 8 00 0x4000 2c00 0x4000 3 000 0x4000 3 400 0x4000 38 00 0x4000 3 c00 0x4000 4400 0x4000 4 8 00 0x4000 4c00 0x4000 5400 0x4000 5 8 00 0x4000 6c00 0x4000 7000 0x4000 7400 0x4001 0000 0x4001 0400 0x4001 0 8 00 0x4001 0c00 0x4001 1000 0x4001 1400 0x4001 1 8 00 0x4001 2400 0x4001 2 8 00 0x4001 2c00 0x4001 3 000 0x4001 3 400 0x4001 38 00 0x4001 3 c00 0x4002 0000 0x4002 0400 0x4002 1000 0x4002 1400 0x4002 2000 0x4002 2400 0x4002 3 000 0x4002 3 400 0xffff ffff re s erved crc re s erved re s erved fla s h interface dma2 re s erved re s erved tim1 re s erved port f dac port d port c port b port a afio pwr bkp i2c2 i2c1 re s erved tim4 tim 3 tim2 0xffff ffff 0xe010 0000 0xe000 0000 0xc000 0000 0xa000 0000 0x 8 000 0000 0x6000 0000 0x4000 0000 0x2000 0000 0x0000 0000 0x1fff ffff 0x1fff f 8 0f 0x1fff f 8 00 0x1fff f000 0x0 8 01 ffff 0x0 8 00 0000 s y s tem memory fla s h memory cortex-m 3 intern a l peripher a l s a i1 8 400 0x0000 0000 alia s ed to fla s h or s y s tem memory dependin g on boot pin s uart4 port e 0x4001 1c00 0x4001 4c00 0x4001 4 8 00 0x4001 4400 0x4001 4000 re s erved tim17 tim16 tim15 0x4000 7c00 0x4000 7 8 00 cec re s erved re s erved 0x4000 5c00 tim6 tim7 tim12 0x4000 1000 0x4000 1400 0x4000 1 8 00 port g 0x4001 2000 0x4000 5000 uart5 s pi 3 tim1 3 tim14 0x4000 1c00 0x4000 2000 f s mc external memory 0x7000 0000 f s mc re gs tim5 electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 34/98 doc id 15081 rev 7 5 electrical characteristics 5.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 5.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 5.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 2v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 5.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 7 . 5.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 8 . stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 35/98 5.1.6 power supply scheme figure 9. power supply scheme caution: in figure 9 , the 4.7 f capacitor must be connected to v dd3 . figure 7. pin loading conditions figure 8. pin input voltage ai14123b c = 50 pf stm32f10xxx pin ai14124b stm32f10xxx pin v in # 55 9 c )) 58 8889 6 #2 &3 0.,. , " 1 0" $% c 76 *, 8 0 : 1 22 & $ ',. ) & #2 d ; 1 0+ 7#$4!$ 1$4 1= ' :.. 7#$4!1 & 0 10+ (# 4!2 & $ 9 e5 a f5ega 5 c &42# 1 c 58 8889 c ))6 c af c a c 6 6)8)6 h 20% b 1 & $ c )) 5 a f5ga c a 5 a f5ga c )) electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 36/98 doc id 15081 rev 7 5.1.7 current con sumption measurement figure 10. current consumption measurement scheme 5.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 6: voltage characteristics , table 7: current characteristics , and table 8: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. ai14126 v bat v dd v dda i dd _v bat i dd table 6. voltage characteristics symbol ratings min max unit v dd ? v ss external main supply voltage (including v dda and v dd ) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connec ted to the external power supply, in the permitted range. ?0.3 4.0 v v in (2) 2. v in maximum must always be respected. refer to table 7: current characteristics for the maximum allowed injected current values. input voltage on five volt tolerant pin v ss ? 0.3 v dd + 4.0 input voltage on any other pin v ss ? 0.3 4.0 | v ddx | variations between different v dd power pins 50 mv |v ssx ? v ss | variations between all the different ground pins 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 5.3.12: absolute maximum ratings (electrical sensitivity) stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 37/98 5.3 operating conditions 5.3.1 general operating conditions table 7. current characteristics symbol ratings max. unit i vdd total current into v dd /v dda power lines (source) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 150 ma i vss total current out of v ss ground lines (sink) (1) 150 i io output current sunk by any i/o and control pin 25 output current source by any i/os and control pin ? 25 i inj(pin) (2) 2. negative injection disturbs the analog performance of the device. see note: on page 82 . injected current on five volt tolerant pins (3) 3. positive injection is not possible on thes e i/os. a negative injection is induced by v in stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 39/98 5.3.3 embedded reset and power control block characteristics the parameters given in ta bl e 1 1 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . . table 11. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.1 2.18 2.26 v pls[2:0]=000 (falling edge) 2 2.08 2.16 v pls[2:0]=001 (rising edge) 2.19 2.28 2.37 v pls[2:0]=001 (falling edge) 2.09 2.18 2.27 v pls[2:0]=010 (rising edge) 2.28 2.38 2.48 v pls[2:0]=010 (falling edge) 2.18 2.28 2.38 v pls[2:0]=011 (rising edge) 2.38 2.48 2.58 v pls[2:0]=011 (falling edge) 2.28 2.38 2.48 v pls[2:0]=100 (rising edge) 2.47 2.58 2.69 v pls[2:0]=100 (falling edge) 2.37 2.48 2.59 v pls[2:0]=101 (rising edge) 2.57 2.68 2.79 v pls[2:0]=101 (falling edge) 2.47 2.58 2.69 v pls[2:0]=110 (rising edge) 2.66 2.78 2.9 v pls[2:0]=110 (falling edge) 2.56 2.68 2.8 v pls[2:0]=111 (rising edge) 2.76 2.88 3 v pls[2:0]=111 (falling edge) 2.66 2.78 2.9 v v pvdhyst (2) pvd hysteresis 100 mv v por/pdr power on/power down reset threshold falling edge 1.8 (1) 1. the product behavior is guaranteed by design down to the minimum v por/pdr value. 1.88 1.96 v rising edge 1.84 1.92 2.0 v v pdrhyst (2) pdr hysteresis 40 mv t rsttempo (2) 2. guaranteed by design, not tested in production. reset temporization 1.5 2.5 4.5 ms electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 40/98 doc id 15081 rev 7 5.3.4 embedded reference voltage the parameters given in ta bl e 1 2 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . 5.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pin loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 10: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to dhrystone 2.1 code. maximum current consumption the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled except if it is explicitly mentioned prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) when the peripherals are enabled f pclk1 = f hclk /2, f pclk2 = f hclk the parameters given in ta bl e 1 3 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . table 12. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.16 1.20 1.26 v ?40 c < t a < +85 c 1.16 1.20 1.24 v t s_vrefint (1) 1. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the internal reference voltage 5.1 17.1 (2) 2. guaranteed by design, not tested in production. s v rerint (2) internal reference voltage spread over the temperature range v dd = 3 v 10 mv 10 mv t coeff (2) temperature coefficient 100 ppm/c stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 41/98 table 13. maximum current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk max (1) 1. based on characterization , not tested in production. unit t a = 85 c t a = 105 c i dd supply current in run mode external clock (2) , all peripherals enabled 2. external clock or hsi frequency is 8 mhz and pll is on when f hclk > 8 mhz. 24 mhz 19.7 20 ma 16 mhz 14.6 14.7 8 mhz 8.2 8.6 external clock (2) , all peripherals disabled 24 mhz 11.3 11.6 16 mhz 8.7 8.9 8 mhz 5.6 6 hsi clock (2) , all peripherals enabled 24 mhz 19 19 16 mhz 13.1 13.2 8 mhz 10.1 10.1 hsi clock (2) , all peripherals disabled 24 mhz 9.4 9.6 16 mhz 6.7 7 8 mhz 5.4 5.6 table 14. maximum current consumption in run mode, code with data processing running from ram symbol parameter conditions f hclk max (1) 1. based on characterization, tested in production at v dd max, f hclk max. unit t a = 85 c t a = 105 c i dd supply current in run mode external clock (2) , all peripherals enabled 2. external clock or hsi frequency is 8 mhz and pll is on when f hclk > 8 mhz. 24 mhz 18.5 19 ma 16 mhz 13.1 13.5 8 mhz 7.3 7.6 external clock (2) all peripherals disabled 24 mhz 8.4 8.5 16 mhz 7.3 7.7 8 mhz 4.8 5.2 hsi clock (2) , all peripherals enabled 24 mhz 17.2 17.2 16 mhz 11.7 11.8 8 mhz 8.9 9 hsi clock (2) , all peripherals disabled 24 mhz 8.1 8.3 16 mhz 5.6 5.8 8 mhz 4.3 4.5 electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 42/98 doc id 15081 rev 7 table 15. stm32f100xxb maximum current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk max (1) 1. based on characterization, tested in production at v dd max and f hclk max with peripherals enabled. unit t a = 85 c t a = 105 c i dd supply current in sleep mode external clock (2) all peripherals enabled 2. external clock or hsi frequency is 8 mhz and pll is on when f hclk > 8 mhz. 24 mhz 14.1 14.3 ma 16 mhz 9.7 10.3 8 mhz 5.9 6.2 external clock (2) , all peripherals disabled 24 mhz 4.2 4.6 16 mhz 3.7 4.1 8 mhz 2.9 3.4 hsi clock (2) , all peripherals enabled 24 mhz 12.5 12.7 16 mhz 8.2 8.5 8 mhz 6.4 6.6 hsi clock (2) , all peripherals disabled 24 mhz 2.3 2.5 16 mhz 1.7 2 8 mhz 1.4 1.7 stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 43/98 typical current consumption the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled except if it is explicitly mentioned when the peripherals are enabled f pclk1 = f hclk /4, f pclk2 = f hclk /2, f adcclk = f pclk2 /4 the parameters given in ta bl e 1 7 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . table 16. typical and maximum current consumptions in stop and standby modes symbol parameter conditions typ (1) max unit v dd /v bat = 2.0 v v dd / v bat = 2.4 v v dd /v bat = 3.3 v t a = 85 c t a = 105 c i dd supply current in stop mode regulator in run mode, low-speed and high-speed internal rc oscillators and high- speed oscillator off (no independent watchdog) 31 320 670 a regulator in low-power mode, low-speed and high-speed internal rc oscillators and high- speed oscillator off (no independent watchdog) 24 305 650 supply current in standby mode low-speed internal rc oscillator and independent watchdog on 3.2 low-speed internal rc oscillator on, independent watchdog off 3.1 low-speed internal rc oscillator and independent watchdog off, low-speed oscillator and rtc off 2.2 3.9 5.7 i dd_vbat backup domain supply current low-speed oscillator and rtc on 1.0 1.2 1.4 2 2.3 1. typical values are measured at t a = 25 c. electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 44/98 doc id 15081 rev 7 table 17. typical current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typical values (1) 1. typical values are measures at t a = 25 c, v dd = 3.3 v. unit all peripherals enabled (2) 2. add an additional power consumption of 0.8 ma for the adc and of 0.5 ma for the dac analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). all peripherals disabled i dd supply current in run mode running on high-speed external clock with an 8 mhz crystal (3) 3. an 8 mhz crystal is used as the ex ternal clock source. the ahb presca ler is used to reduce the frequency when f hclk < 8 mhz, the pll is used when f hclk > 8 mhz. 24 mhz 14.1 9.5 ma 16 mhz 10 6.85 8 mhz 5.8 4.05 4 mhz 3.6 2.65 2 mhz 2.3 1.85 1 mhz 1.7 1.46 500 khz 1.4 1.3 125 khz 1.15 1.1 running on high-speed internal rc (hsi) 24 mhz 13.4 8.7 16 mhz 9.3 6.2 8 mhz 5.2 3.45 4 mhz 2.95 2.1 2 mhz 1.7 1.3 1 mhz 1.1 0.9 500 khz 0.8 0.7 125 khz 0.6 0.55 stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 45/98 table 18. typical current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk typical values (1) 1. typical values are measures at t a = 25 c, v dd = 3.3 v. unit all peripherals enabled (2) 2. add an additional power consumption of 0.8 ma for the adc and of 0.5 ma for the dac analog part. in applications, this consumpti on occurs only while the adc is on (adon bit is set in the adc_cr2 register). all peripherals disabled i dd supply current in sleep mode running on high-speed external clock with an 8 mhz crystal (3) 3. an 8 mhz crystal is used as the external clock source. the ahb pre scaler is used to reduce the frequency when f hclk > 8 mhz, the pll is used when f hclk > 8 mhz. 24 mhz 8.7 2.75 ma 16 mhz 6.1 2.1 8 mhz 3.3 1.3 4 mhz 2.25 1.2 2 mhz 1.65 1.15 1 mhz 1.35 1.1 500 khz 1.2 1.07 125 khz 1.1 1.05 running on high-speed internal rc (hsi) 24 mhz 8 2.15 16 mhz 5.5 1.5 8 mhz 2.7 0.75 4 mhz 1.65 0.6 2 mhz 1.1 0.55 1 mhz 0.8 0.5 500 khz 0.65 0.49 125 khz 0.53 0.47 electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 46/98 doc id 15081 rev 7 on-chip peripheral current consumption the current consumption of the on-chip peripherals is given in ta bl e 1 9 . the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ambient operating temperature and v dd supply voltage conditions summarized in ta bl e 6 . table 19. peripheral current consumption peripheral typical consumption at 25 c (1) unit apb1 tim2 0.48 ma tim3 0.49 tim4 0.48 tim5 0.48 tim6 0.2 tim7 0.2 tim12 0.32 tim13 0.25 tim14 0.25 dac 1.06 (2) wwdg 0.15 spi2 0.2 spi3 0.19 usart2 0.36 usart3 0.36 uart4 0.35 uart5 0.36 i2c1 0.34 i2c2 0.34 hdmi cec 0.2 stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 47/98 5.3.6 external cloc k source characteristics high-speed external user clock generated from an external source the characteristics given in ta b l e 2 0 result from tests performed using an high-speed external clock source, and under the ambient temperature and supply voltage conditions summarized in ta b l e 9 . apb2 gpio a 0.26 ma gpio b 0.26 gpio c 0.26 gpio d 0.26 gpio e 0.26 gpio f 0.24 gpio g 0.25 adc1 (3) 1.28 spi1 0.2 usart1 0.37 tim1 0.63 tim15 0.43 tim16 0.34 tim17 0.34 1. f hclk = f apb1 = f apb2 = 24 mhz, default prescaler value for each peripheral. 2. specific conditions for dac: en 1 bit in dac_cr register set to 1. 3. specific conditions for adc: f hclk = 24 mhz, f apb1 = f apb2 = f hclk , f adcclk = f apb2 /2, adon bit in the adc_cr2 register is set to 1. table 19. peripheral current consumption (continued) peripheral typical consumption at 25 c (1) unit table 20. high-speed external user clock characteristics symbol parameter conditions min typ max unit f hse_ext user external clock source frequency (1) 1824mhz v hseh osc_in input pin high level voltage (1) 0.7v dd v dd v v hsel osc_in input pin low level voltage (1) v ss 0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 5 ns t r(hse) t f(hse) osc_in rise or fall time (1) 20 c in(hse) osc_in input capacitance (1) 5pf electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 48/98 doc id 15081 rev 7 low-speed external user clock generated from an external source the characteristics given in ta b l e 2 1 result from tests performed using an low-speed external clock source, and under the ambient temperature and supply voltage conditions summarized in ta b l e 9 . ducy (hse) duty cycle (1) 45 55 % i l osc_in input leakage current v ss v in v dd 1 a 1. guaranteed by design, not tested in production. table 21. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. 32.768 1000 khz v lseh osc32_in input pin high level voltage (1) 0.7v dd v dd v v lsel osc32_in input pin low level voltage (1) v ss 0.3v dd t w(lse) t w(lse) osc32_in high or low time (1) 450 ns t r(lse) t f(lse) osc32_in rise or fall time (1) 50 c in(lse) osc32_in input capacitance (1) 5pf ducy (lse) duty cycle (1) 30 70 % i l osc32_in input leakage current v ss v in v dd 1 a table 20. high-speed external user clock characteristics symbol parameter conditions min typ max unit stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 49/98 figure 11. high-speed external clock source ac timing diagram figure 12. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 24 mhz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 2 2 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). ai14127b os c _i n external stm32f10xxx clock source v hseh t f(hse) t w(hse) i l 90% 10% t hse t t r(hse) t w(hse) f hse_ext v hsel ai14140c osc32_in external stm32f10xxx clock source v lseh t f(lse) t w(lse) i l 90% 10% t lse t t r(lse) t w(lse) f lse_ext v lsel electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 50/98 doc id 15081 rev 7 figure 13. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 2 3 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). table 22. hse 4-24 mhz oscillator characteristics (1)(2) 1. resonator characte ristics given by the crystal/ ceramic resonator manufacturer. 2. based on characterization , not tested in production. symbol parameter conditions min typ max unit f osc_in oscillator frequency 4 8 24 mhz r f feedback resistor 200 k c l1 c l2 (3) 3. it is recommended to use high-qualit y external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-frequency applications, and selected to match th e requirements of the crystal or resonator. c l1 and c l2, are usually the same size. the crystal manufacturer typica lly specifies a load capacitance which is the se ries combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a r ough estimate of the combined pin and board capacitance) when sizing c l1 and c l2 . recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (4) 4. the relatively low value of the rf resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and t he bias condition change. however, it is recommended to take this point into account if the mcu is used in tough humidity conditions. r s = 30 30 pf i 2 hse driving current v dd = 3.3 v v in = v ss with 30 pf load 1ma g m oscillator transconductance startup 25 ma/v t su(hse) (5) 5. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonat or and it can vary significantly with the crystal manufacturer startup time v dd is stabilized 2 ms ai14128b osc_ou t osc_in f hse c l1 r f stm32f10xxx 8 mh z resonator resonator with integrated capacitors bias controlled gain r ext (1) c l2 stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 51/98 note: for c l1 and c l2 it is recommended to use high-quality ceramic capacitors in the 5 pf to 15 pf range selected to match the requirements of the crystal or resonator. c l1 and c l2, are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . load capacitance c l has the following formula: c l = c l1 x c l2 / ( c l1 + c l2 ) + c stray where c stray is the pin capacitance and board or trace pcb-related capacitance. typically, it is between 2 pf and 7 pf. caution: to avoid exceeding the maximum value of c l1 and c l2 (15 pf) it is strongly recommended to use a resonator with a load capacitance c l 7 pf. never use a resonator with a load capacitance of 12.5 pf. example: if you choose a resonator with a load capacitance of c l = 6 pf, and c stray = 2 pf, then c l1 = c l2 = 8 pf. table 23. lse oscillator characteristics (f lse = 32.768 khz) (1) symbol parameter conditions min typ max unit r f feedback resistor 5 m c l1 c l2 (2) recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (3) r s = 30 k 15 pf i 2 lse driving current v dd = 3.3 v v in = v ss 1.4 a g m oscillator transconductance 5 a/v t su(lse) (4) startup time v dd is stabilized t a = 50 c 1.5 s t a = 25 c 2.5 t a = 10 c 4 t a = 0 c 6 t a = -10 c 10 t a = -20 c 17 t a = -30 c 32 t a = -40 c 60 1. based on characterization, not tested in production. 2. refer to the note and caution paragraphs above the table. 3. the oscillator selection c an be optimized in terms of supply current using an high quality resonator with small r s value for example msiv-tin32.768 khz. refer to crystal manufacturer for more details 4. t su(lse) is the startup time measured from the moment it is enab led (by software) to a stabili zed 32.768 khz oscillation is reached. this value is measured for a standard crystal and it can vary significantly wi th the crystal manufacturer electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 52/98 doc id 15081 rev 7 figure 14. typical application with a 32.768 khz crystal 5.3.7 internal clock source characteristics the parameters given in ta bl e 2 4 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . high-speed internal (hsi) rc oscillator low-speed internal (lsi) rc oscillator ai14129b osc32_ou t osc32_in f lse c l1 r f stm32f10xxx 32.768 kh z resonator resonator with integrated capacitors bias controlled gain c l2 table 24. hsi oscillator characteristics (1) 1. v dd = 3.3 v, t a = ?40 to 105 c c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency 8 mhz acc hsi accuracy of hsi oscillator t a = ?40 to 105 c (2) 2. based on characterization , not tested in production. -2.4 2.5 % t a = ?10 to 85 c (2) -2.2 1.3 % t a = 0 to 70 c (2) -1.9 1.3 % t a = 25 c -1 1 % t su(hsi) (3) 3. guaranteed by design. not tested in production hsi oscillator startup time 1 2 s i dd(hsi) (3) hsi oscillator power consumption 80 100 a table 25. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = ?40 to 105 c c unless otherwise specified. symbol parameter min typ max unit f lsi frequency 30 40 60 khz t su(lsi) (2) 2. guaranteed by design, not tested in production. lsi oscillator startup time 85 s i dd(lsi) (2) lsi oscillator power consumption 0.65 1.2 a stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 53/98 wakeup time from low-power mode the wakeup times given in ta b l e 2 6 are measured on a wakeup phase with an 8-mhz hsi rc oscillator. the clock source used to wake up the device depends from the current operating mode: stop or standby mode: the cloc k source is the rc oscillator sleep mode: the clock source is the clock that was set before entering sleep mode. all timings are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta bl e 9 . 5.3.8 pll characteristics the parameters given in ta bl e 2 7 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . table 26. low-power mode wakeup timings symbol parameter typ unit t wusleep (1) 1. the wakeup times are measured from the wakeup even t to the point at which the user application code reads the first instruction. wakeup from sleep mode 1.8 s t wustop (1) wakeup from stop mode (regulator in run mode) 3.6 s wakeup from stop mode (regulator in low-power mode) 5.4 t wustdby (1) wakeup from standby mode 50 s table 27. pll characteristics symbol parameter value unit min (1) typ max (1) 1. based on device characteriza tion, not tested in production. f pll_in pll input clock (2) 2. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . 18.024mhz pll input clock duty cycle 40 60 % f pll_out pll multiplier output clock 16 24 mhz t lock pll lock time 200 s jitter cycle-to-cycle jitter 300 ps electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 54/98 doc id 15081 rev 7 5.3.9 memory characteristics flash memory the characteristics are given at t a = ?40 to 105 c unless otherwise specified. 5.3.10 fsmc characteristics asynchronous waveforms and timings figure 15 through figure 18 represent asynchronous waveforms and ta b l e 3 0 through ta bl e 3 3 provide the corresponding timings. the results shown in these tables are obtained with the following fsmc configuration: addresssetuptime = 0 addressholdtime = 1 datasetuptime = 1 table 28. flash memory characteristics symbol parameter conditions min (1) 1. guaranteed by design, not tested in production. typ max (1) unit t prog 16-bit programming time t a = ?40 to +105 c 40 52.5 70 s t erase page (2 kb) erase time t a = ?40 to +105 c 20 40 ms t me mass erase time t a = ?40 to +105 c 20 40 ms i dd supply current read mode f hclk = 24 mhz, v dd = 3.3 v 20 ma write / erase modes f hclk = 24 mhz, v dd = 3.3 v 5ma power-down mode / halt, v dd = 3.0 to 3.6 v 50 a v prog programming voltage 2 3.6 v table 29. flash memory endurance and data retention symbol parameter conditions value unit min (1) 1. based on characterization not tested in production. typ max n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over t he whole temperature range. 30 ye a r s 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20 stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 55/98 figure 15. asynchronous non-multiplexed sram/psram/nor read waveforms 1. mode 2/b, c and d only. in mode 1, fsmc_nadv is not used. )## a a 7?53@ a )?593@ h'7 + %')## + a 6 1 00 a 6? 93@ h'6 + a ( 04')## + '+ 59c5 "'+ h' + %' + %')## + %'6 + %'7 + 04')## + a 6)c '5+ h'6)c + "'6)c+ electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 56/98 doc id 15081 rev 7 table 30. asynchronous non-multiplexed sram/psram/nor read timings (1) (2) 1. c l = 15 pf. 2. preliminary values. symbol parameter min max unit t w(ne) fsmc_ne low time 5t hclk ? 1.5 5t hclk + 2 ns t v(noe_ne) fsmc_nex low to fsmc_noe low 0.5 1.5 ns t w(noe) fsmc_noe low time 5t hclk ? 1.5 5t hclk + 1.5 ns t h(ne_noe) fsmc_noe high to fsmc_ne high hold time ?1.5 ns t v(a_ne) fsmc_nex low to fsmc_a valid 0 ns t h(a_noe) address hold time after fsmc_noe high 0.1 ns t v(bl_ne) fsmc_nex low to fsmc_bl valid 0 ns t h(bl_noe) fsmc_bl hold time after fsmc_noe high 0 ns t su(data_ne) data to fsmc_nex high setup time 2t hclk + 25 ns t su(data_noe) data to fsmc_noex high setup time 2t hclk + 25 ns t h(data_noe) data hold time after fsmc_noe high 0 ns t h(data_ne) data hold time after fsmc_nex high 0 ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low 5 ns t w(nadv) fsmc_nadv low time t hclk + 1.5 ns stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 57/98 figure 16. asynchronous non-multiplexed sram/psram/nor write waveforms 1. mode 2/b, c and d only. in mode 1, fsmc_nadv is not used. table 31. asynchronous non-multiplexed sram/psram/nor write timings (1)(2) 1. c l = 15 pf. 2. preliminary values. symbol parameter min max unit t w(ne) fsmc_ne low time 3t hclk ? 1 3t hclk + 2 ns t v(nwe_ne) fsmc_nex low to fsmc_nwe low t hclk ? 0.5 t hclk + 1.5 ns t w(nwe) fsmc_nwe low time t hclk ? 0.5 t hclk + 1.5 ns t h(ne_nwe) fsmc_nwe high to fsmc_ne high hold time t hclk ns t v(a_ne) fsmc_nex low to fsmc_a valid 7.5 ns t h(a_nwe) address hold time after fsmc_nwe high t hclk ns t v(bl_ne) fsmc_nex low to fsmc_bl valid 1.5 ns t h(bl_nwe) fsmc_bl hold time after fsmc_nwe high t hclk ? 0.5 ns t v(data_ne) fsmc_nex low to data valid t hclk + 7 ns t h(data_nwe) data hold time afte r fsmc_nwe high t hclk ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low 5.5 ns t w(nadv) fsmc_nadv low time t hclk + 1.5 ns nbl data fsmc_nex fsmc_nbl[1:0] fsmc_d[15:0] t v(bl_ne) t h(data_nwe) fsmc_noe address fsmc_a[25:0] t v(a_ne) t w(nwe) fsmc_nwe t v(nwe_ne) t h(ne_nwe) t h(a_nwe) t h(bl_nwe) t v(data_ne) t w(ne) ai14990 fsmc_nadv (1) t v(nadv_ne) t w(nadv) electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 58/98 doc id 15081 rev 7 figure 17. asynchronous multiplexed psram/nor read waveforms table 32. asynchronous multiplexed psram/nor read timings (1)(2) 1. c l = 15 pf. 2. preliminary values. symbol parameter min max unit t w(ne) fsmc_ne low time 7t hclk ? 2 7t hclk + 2 ns t v(noe_ne) fsmc_nex low to fsmc_noe low 3t hclk ? 0.5 3t hclk + 1.5 ns t w(noe) fsmc_noe low time 4t hclk ? 1 4t hclk + 2 ns t h(ne_noe) fsmc_noe high to fsmc_ne high hold time ?1 ns t v(a_ne) fsmc_nex low to fsmc_a valid 0 ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low 3 5 ns t w(nadv) fsmc_nadv low time t hclk ?1.5 t hclk + 1.5 ns t h(ad_nadv) fsmc_ad (address) valid hold time after fsmc_nadv high t hclk ns t h(a_noe) address hold time after fsmc_noe high t hclk ns t h(bl_noe) fsmc_bl hold time after fsmc_noe high 0 ns t v(bl_ne) fsmc_nex low to fsmc_bl valid 0 ns t su(data_ne) data to fsmc_nex high setup time 2t hclk + 24 ns t su(data_noe) data to fsmc_noe high setup time 2t hclk + 25 ns t h(data_ne) data hold time after fsmc_nex high 0 ns t h(data_noe) data hold time after fsmc_noe high 0 ns nbl data fsmc_nbl[1:0] fsmc_ ad[15:0] t v(bl_ne) t h(data_ne) address fsmc_a[25:16] t v(a_ne) fsmc_nwe t v(a_ne) ai14892b address fsmc_nadv t v(nadv_ne) t w(nadv) t su(data_ne) t h(ad_nadv) fsmc_ne fsmc_noe t w(ne) t w(noe) t v(noe_ne) t h(ne_noe) t h(a_noe) t h(bl_noe) t su(data_noe) t h(data_noe) stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 59/98 figure 18. asynchronous multiplexed psram/nor write waveforms table 33. asynchronous multiplexed psram/nor write timings (1)(2) 1. c l = 15 pf. 2. preliminary values. symbol parameter min max unit t w(ne) fsmc_ne low time 5t hclk ? 1 5t hclk + 2 ns t v(nwe_ne) fsmc_nex low to fsmc_nwe low 2t hclk 2t hclk + 1 ns t w(nwe) fsmc_nwe low time 2t hclk ? 1 2t hclk + 2 ns t h(ne_nwe) fsmc_nwe high to fsmc_ne high hold time t hclk ? 1 ns t v(a_ne) fsmc_nex low to fsmc_a valid 7 ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low 3 5 ns t w(nadv) fsmc_nadv low time t hclk ? 1 t hclk + 1 ns t h(ad_nadv) fsmc_ad (address) valid hold time after fsmc_nadv high t hclk ? 3 ns t h(a_nwe) address hold time after fsmc_nwe high 4t hclk ns t v(bl_ne) fsmc_nex low to fsmc_bl valid 1.6 ns t h(bl_nwe) fsmc_bl hold time after fsmc_nwe high t hclk ? 1.5 ns t v(data_nadv) fsmc_nadv high to data valid t hclk + 1.5 ns t h(data_nwe) data hold time after fsmc_nwe high t hclk ? 5 ns nbl data fsmc_nex fsmc_nbl[1:0] fsmc_ ad[15:0] t v(bl_ne) t h(data_nwe) fsmc_noe address fsmc_a[25:16] t v(a_ne) t w(nwe) fsmc_nwe t v(nwe_ne) t h(ne_nwe) t h(a_nwe) t h(bl_nwe) t v(a_ne) t w(ne) ai14891b address fsmc_nadv t v(nadv_ne) t w(nadv) t v(data_nadv) t h(ad_nadv) electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 60/98 doc id 15081 rev 7 synchronous waveforms and timings figure 19 through figure 22 represent synchronous waveforms and ta bl e 3 5 through ta bl e 3 7 provide the corresponding timings. the results shown in these tables are obtained with the following fsmc configuration: burstaccessmode = fsmc_burstaccessmode_enable; memorytype = fsmc_memorytype_cram; writeburst = fsmc_writeburst_enable; clkdivision = 1; (0 is not supported, see the stm32f10xxx reference manual) datalatency = 1 for nor flash; datalatency = 0 for psram figure 19. synchronous multiplexed nor/psram read timings a : a - a 6)c a 6? 935@ a a 6)?593@ 6)?593@ )5 ) a (6 '(6a*/5<.(6,f<+ a (6 '(6a*/<.(6,f<+ "':+ "':+ )##2# $=/ 7/ ': -+ ': -+ ': 6)c+ ': 6c+ ': 6)c+ ': 6c+ ': + ': + ': 6)c+ ': 6)c+ 04'6)c :+ %': 6)c+ 04'6)c :+ %': 6)c+ 04'(6c :+ %': (6c+ 04'(6c :+ %': (6c+ 04'(6c :+ %': (6c+ # 5i ) stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 61/98 table 34. synchronous multiplexed nor/psram read timings (1)(2) 1. c l = 15 pf. 2. preliminary values. symbol parameter min max unit t w(clk) fsmc_clk period 27.7 ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x = 0...2) 1.5 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x = 0...2) 2 ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low 4 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 5 ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x = 16...25) 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x = 16...25) 2 ns t d(clkh-noel) fsmc_clk high to fsmc_noe low 1 ns t d(clkl-noeh) fsmc_clk low to fsmc_noe high 0.5 ns t d(clkl-adv) fsmc_clk low to fsmc_ad[15:0] valid 12 ns t d(clkl-adiv) fsmc_clk low to fsmc_ad[15:0] invalid 0 ns t su(adv-clkh) fsmc_a/d[15:0] valid data before fsmc_clk high 6 ns t h(clkh-adv) fsmc_a/d[15:0] valid data after fsmc_clk high 0 ns t su(nwaitv-clkh) fsmc_nwait valid before fsmc_clk high 8 ns t h(clkh-nwaitv) fsmc_nwait valid after fsmc_clk high 2 ns electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 62/98 doc id 15081 rev 7 figure 20. synchronous multiplexed psram write timings a : a - a 6)c a 6? 935@ a ( a 6)?593@ 6)?593@ )5 ) a (6 '(6a*/<.(6,f<+ "':+ "':+ )##2# $=/ 7/ ': -+ ': -+ ': 6)c+ ': 6c+ ': 6)c+ ': 6c+ ': (+ ': (+ ': 7+ ': 6)c+ ': 6)c+ ': )##+ 04'(6c :+ %': (6c+ # 5ii % ': )##+ a 7 stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 63/98 table 35. synchronous multiplexed psram write timings (1)(2) 1. c l = 15 pf. 2. preliminary values symbol parameter min max unit t w(clk) fsmc_clk period 27.7 ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x = 0...2) 2 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x = 0...2) 2 ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low 4 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 5 ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x = 16...25) 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x = 16...25) 2 ns t d(clkl-nwel) fsmc_clk low to fsmc_nwe low 1 ns t d(clkl-nweh) fsmc_clk low to fsmc_nwe high 1 ns t d(clkl-adv) fsmc_clk low to fsmc_ad[15:0] valid 12 ns t d(clkl-adiv) fsmc_clk low to fsmc_ad[15:0] invalid 3 ns t d(clkl-data) fsmc_a/d[15:0] valid after fsmc_clk low 6 ns t su(nwaitv-clkh) fsmc_nwait valid before fsmc_clk high 7 ns t h(clkh-nwaitv) fsmc_nwait valid after fsmc_clk high 2 ns t d(clkl-nblh) fsmc_clk low to fsmc_nbl high 1 ns electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 64/98 doc id 15081 rev 7 figure 21. synchronous non-multiplexed nor/psram read timings table 36. synchronous non-multiplexed nor/psram read timings (1)(2) 1. c l = 15 pf. 2. preliminary values. symbol parameter min max unit t w(clk) fsmc_clk period 27.7 ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x = 0...2) 1.5 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x = 0...2) 2 ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low 4 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 5 ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x = 0...25) 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x = 0...25) 4 ns t d(clkh-noel) fsmc_clk high to fsmc_noe low 1.5 ns t d(clkl-noeh) fsmc_clk low to fsmc_noe high 1.5 ns t su(dv-clkh) fsmc_d[15:0] valid data bef ore fsmc_clk high 6.5 ns t h(clkh-dv) fsmc_d[15:0] valid data after fsmc_clk high 7 ns t su(nwaitv-clkh) fsmc_nwait valid before fsmc_smclk high 7 ns t h(clkh-nwaitv) fsmc_nwait valid after fsmc_clk high 2 ns a : a - a 6? 93@ a a )?593@ )5 ) a (6 '(6a*/5<.(6,f<+ a (6 '(6a*/<.(6,f<+ "':+ "':+ )##2# $=/ 7/ ': -+ ': -+ ': 6c+ ': 6c+ ': + ': + 04')c :+ %': )c+ 04')c :+ %': )c+ 04'(6c :+ %': (6c+ 04'(6c :+ %': (6c+ 04'(6c :+ %': (6c+ # 5i% a 6)c ': 6)c+ ': 6)c+ ) stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 65/98 figure 22. synchronous non-multiplexed psram write timings table 37. synchronous non-multiplexed psram write timings (1)(2) 1. c l = 15 pf. 2. preliminary values. symbol parameter min max unit t w(clk) fsmc_clk period 27.7 ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x = 0...2) 2 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x = 0...2) 2 ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low 4 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 5 ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x = 16...25) 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x = 16...25) 2 ns t d(clkl-nwel) fsmc_clk low to fsmc_nwe low 1 ns t d(clkl-nweh) fsmc_clk low to fsmc_nwe high 1 ns t d(clkl-data) fsmc_d[15:0] valid data after fsmc_clk low 6 ns t su(nwaitv-clkh) fsmc_nwait valid before fsmc_clk high 7 ns t h(clkh-nwaitv) fsmc_nwait valid after fsmc_clk high 2 ns t d(clkl-nblh) fsmc_clk low to fsmc_nbl high 1 ns a : a - a 6? 93@ a ( a )?593@ )5 ) a (6 '(6a*/<.(6,f<+ "':+ "':+ )##2# $=/ 7/ ': -+ ': -+ ': 6c+ ': 6c+ ': (+ ': (+ ': )##+ 04'(6c :+ %': (6c+ # 5ii a 6)c ': 6)c+ ': 6)c+ ': )##+ a 7 ': 7+ electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 66/98 doc id 15081 rev 7 5.3.11 emc characteristics susceptibility tests ar e performed on a sample basis during device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in ta b l e 3 8 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and pre qualification tests in rela tion with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 38. ems characteristics symbol parameter conditions level/class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, t a = +25 c, f hclk = 24 mhz, lqfp144 package, conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, t a = +25 c, f hclk = 24 mhz, lqfp144 package, conforms to iec 61000-4-4 4a stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 67/98 electromagnetic interference (emi) the electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 leds through the i/o ports). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 5.3.12 absolute maximum rati ngs (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determine its perfor mance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. static latch-up two complementary static tests are required on six parts to assess the latch-up performance: a supply overvoltage is applied to each power supply pin a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd78 ic latch-up standard. table 39. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/24 mhz s emi peak level v dd = 3.6 v, t a = 25c, lqfp144 package compliant with sae j1752/3 0.1 mhz to 30 mhz 16 dbv 30 mhz to 130 mhz 25 130 mhz to 1ghz 25 sae emi level 4 - table 40. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c conforming to jesd22-a114 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c conforming to jesd22-c101 ii 500 table 41. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78 ii level a electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 68/98 doc id 15081 rev 7 5.3.13 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection a ccidentally happens, susceptibilit y tests are performed on a sample basis during device characterization. functional susceptibilty to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode. while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (>5 lsb tue), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). the test results are given in ta b l e 4 2 table 42. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on osc_in32, osc_out32, pa4, pa5, pc13 -0 +0 ma injected current on all ft pins -5 +0 injected current on any other pin -5 +5 stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 69/98 5.3.14 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in ta bl e 4 3 are derived from tests performed under the conditions summarized in ta b l e 9 . all i/os are cmos and ttl compliant. all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 23 and figure 24 for standard i/os, and in figure 25 and figure 26 for 5 v tolerant i/os. table 43. i/o static characteristics symbol parameter conditions min typ max unit v il standard i/o input low level voltage ?0.3 0.28*(v dd ?2 v)+0.8 v v i/o ft (1) input low level voltage ?0.3 0.32*(v dd ?2 v)+0.75 v v ih standard i/o input high level voltage 0.41*(v dd ?2 v) +1.3 v v dd +0.3 i/o ft (1) input high level voltage v dd > 2 v 0.42*(v dd ?2)+1 v 5.5 v dd 2 v 5.2 v hys standard i/o schmitt trigger voltage hysteresis (2) 200 mv i/o ft schmitt trigger voltage hysteresis (2) 5% v dd (3) mv i lkg input leakage current (4) v ss v in v dd standard i/os 1 a v in = 5 v i/o ft 3 r pu weak pull-up equivalent resistor (5) v in = v ss 30 40 50 k r pd weak pull-down equivalent resistor (5) v in = v dd 30 40 50 k c io i/o pin capacitance 5 pf 1. ft = 5v tolerant. to sustain a voltage higher than v dd +0.3 the internal pull-up/pull- down resistors must be disabled. 2. hysteresis voltage between schmitt trigger switchin g levels. guaranteed by design, not tested in production. 3. with a minimum of 100 mv. 4. leakage could be higher than max. if negativ e current is injected on adjacent pins. 5. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this pmos/nmos contribution to the series resistance is minimum (~10% order) . electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 70/98 doc id 15081 rev 7 figure 23. standard i/o input characteristics - cmos port figure 24. standard i/o input characteristics - ttl port # 5 < c )) 'c+ 5 !41# & &4#1# 59i 5 c /5'c )) +f5 0# #1 1 j4 1 ; c /9c )) c 8c 'c+ 0# #1 1 j4 1 ; c /9c )) 7 ;#- 7 ; c )) +f / 'c # 5 !41# & &4#1# c 8c 'c+ 5 5 5i 5 9 1 j4 1 ; 0 c / c c /5'c )) +f5 c / 'c )) +f 1 j4 1 ; 0 c /c c )) 'c+ 7 ;#- 7 ; stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 71/98 figure 25. 5 v tolerant i/o input characteristics - cmos port figure 26. 5 v tolerant i/o input characteristics - ttl port output driving current the gpios (general purpose input/outputs) can sink or source up to +/-8 ma, and sink or source up to +/- 20 ma (with a relaxed vol/voh) except pc13, pc14 and pc15 it can sink or source up to +/-3ma. when using the gpios pc13 to pc15 in output mode, the speed should not exceed 2 mhz with a maximum load of 30 pf. in the user application, the number of i/o pins which can drive current must be limited to respect the absolute maxi mum rating specified in section 5.2 : the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see ta bl e 7 ). the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see ta b l e 7 ). c)) 5 0# #1 1 j4 1 ; 0c /9c )) 0# #1 1 j4 1; c /9c )) 5 5 5 9 5 i9 i9 5 5 599 55 c 8c 'c+ c )) 'c+ !41# & &4#1# # 5 i< c / 'c )) +f5 c / 'c )) +f9 5 &4#1# !41# & 5 5 9 1 j4 1 ; c / c c / k'c )) +f5 c / k'c )) +f9 1 j4 1 ; 0c /c c 8c 'c+ c )) 'c+ 7 ;#- 7 ; # 5 electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 72/98 doc id 15081 rev 7 output voltage levels unless otherwise specified, the parameters given in ta bl e 4 4 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . all i/os are cmos and ttl compliant. table 44. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always re spect the absolute maximu m rating specified in table 7 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin when 8 pins are sunk at the same time cmos port (2) , i io = +8 ma, 2.7 v < v dd < 3.6 v 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. 0.4 v v oh (3) 3. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 7 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin when 8 pins are sourced at the same time v dd ?0.4 v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at the same time ttl port (2) i io = +8 ma 2.7 v < v dd < 3.6 v 0.4 v v oh (3) output high level voltage for an i/o pin when 8 pins are sourced at the same time 2.4 v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at the same time i io = +20 ma (4) 2.7 v < v dd < 3.6 v 4. based on characterization data, not tested in production. 1.3 v v oh (3) output high level voltage for an i/o pin when 8 pins are sourced at the same time v dd ?1.3 v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at the same time i io = +6 ma (4) 2 v < v dd < 2.7 v 0.4 v v oh (3) output high level voltage for an i/o pin when 8 pins are sourced at the same time v dd ?0.4 stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 73/98 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 27 and ta bl e 4 5 , respectively. unless otherwise specified, the parameters given in ta bl e 4 5 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . table 45. i/o ac characteristics (1) 1. the i/o speed is configured using the modex[1:0] bits. refer to t he stm32f100xx reference manual for a description of gpio port configuration register. modex [1:0] bit value (1) symbol parameter conditions max unit 10 f max(io)out maximum frequency (2) 2. the maximum frequency is defined in figure 27 . c l = 50 pf, v dd = 2 v to 3.6 v 2 (3) mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v 125 (3) 3. guaranteed by design, not tested in production. ns t r(io)out output low to high level rise time 125 (3) 01 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v 10 (3) mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v 25 (3) ns t r(io)out output low to high level rise time 25 (3) 11 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v 24 mhz t f(io)out output high to low level fall time c l = 30 pf, v dd = 2.7 v to 3.6 v 5 (3) ns c l = 50 pf, v dd = 2.7 v to 3.6 v 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v 12 (3) t r(io)out output low to high level rise time c l = 30 pf, v dd = 2.7 v to 3.6 v 5 (3) c l = 50 pf, v dd = 2.7 v to 3.6 v 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v 12 (3) -t extipw pulse width of external signals detected by the exti controller 10 (3) ns electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 74/98 doc id 15081 rev 7 figure 27. i/o ac characteristics definition 5.3.15 nrst pin characteristics the nrst pin input driver uses cmos techno logy. it is connected to a permanent pull-up resistor, r pu (see ta bl e 4 3 ). unless otherwise specified, the parameters given in ta bl e 4 6 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . figure 28. recommended nrst pin protectio n 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 46 . otherwise the reset will not be taken into account by the device. ai14131 10% 90% 50% t r(io)out output ext ernal on 50pf maximum frequency is achieved if (t r + t f ) ?? 2/3)t and if the duty cycle is (45-55%) ? 10 % 50% 90% when loaded by 50pf t t r(io)out table 46. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) 1. guaranteed by design, not tested in production. nrst input low level voltage ?0.5 0.8 v v ih(nrst) (1) nrst input high level voltage 2 v dd +0.5 v hys(nrst) nrst schmitt trigger voltage hysteresis 200 mv r pu weak pull-up equivalent resistor (2) 2. the pull-up is designed with a true re sistance in series with a switc hable pmos. this pmos contribution to the series resistance must be minimum (~10% order) . v in = v ss 30 40 50 k v f(nrst) (1) nrst input filtered pulse 100 ns v nf(nrst) (1) nrst input not filtered pulse 300 ns # 55 a5- , ' + c )) a 2 1 1 #21 0 5ga - 1 #2 1 0 $ 1$4 '5+ stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 75/98 5.3.16 timx characteristics the parameters given in ta bl e 4 7 are guaranteed by design. refer to section 5.3.13: i/o current injection characteristics for details on the input/output alternate function characteristics (output co mpare, input capture, external clock, pwm output). 5.3.17 communications interfaces i 2 c interface characteristics unless otherwise specified, the parameters given in ta bl e 4 8 are preliminary values derived from tests performed under the ambient temperature, f pclk1 frequency and v dd supply voltage conditions summarized in ta bl e 9 . the stm32f100xx value line i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: t he i/o pins sda and scl are mapped to are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in ta b l e 4 8 . refer also to section 5.3.13: i/o current injection characteristics for more details on the input/output alternate function characteristics (sda and scl) . table 47. timx characteristics symbol parameter conditions (1) 1. timx is used as a general term to refer to the tim1, tim2, tim3, tim4, tim5, tim15, tim16 and tim17 timers. min max unit t res(tim) timer resolution time 1t timxclk f timxclk = 24 mhz 41.7 ns f ext timer external clock frequency on chx (2) 2. chx is used as a general term to refer to ch1 to ch4 for tim1, tim2, tim3, tim4 and tim5, to the ch1 to ch2 for tim15, and to ch1 for tim16 and tim17. 0f timxclk /2 mhz f timxclk = 24 mhz 0 12 mhz res tim timer resolution 16 bit t counter 16-bit counter clock period when the internal clock is selected 1 65536 t timxclk f timxclk = 24 mhz 2730 s t max_count maximum possible count 65536 65536 t timxclk f timxclk = 24 mhz 178 s electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 76/98 doc id 15081 rev 7 table 48. i 2 c characteristics symbol parameter standard mode i 2 c (1) 1. guaranteed by design, not tested in production. fast mode i 2 c (1) (2) 2. f pclk1 must be at least 2 mhz to achieve standard mode i 2 c frequencies. it must be at least 4 mhz to achieve fast mode i 2 c frequencies. it must be a multiple of 10 mhz to reach the 400 khz maximum i2c fast mode clock. unit min max min max t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 0 900 (3) 3. the maximum data hold time has only to be met if t he interface does not stretch the low period of scl signal. t r(sda) t r(scl) sda and scl rise time 1000 300 t f(sda) t f(scl) sda and scl fall time 300 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 s c b capacitive load for each bus line 400 400 pf stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 77/98 figure 29. i 2 c bus ac waveforms and measurement circuit 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . table 49. scl frequency (f pclk1 = 24 mhz, v dd = 3.3 v) (1)(2) 1. r p = external pull-up resistance, f scl = i 2 c speed, 2. for speeds around 400 khz, the tole rance on the achieved speed is of 2%. for other speed ranges, the tolerance on the achieved speed 1%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) (3) 3. guaranteed by design, not tested in production. i2c_ccr value r p = 4.7 k 400 0x8011 300 0x8016 200 0x8021 100 0x0064 50 0x00c8 20 0x01f4 # 55 #1 ) 6 5 ! ! l<40 ! 5 ! c )) c )) a5- )6 b')6+ 1')6+ %'6+ "'+ "'+ 04')6+ 1'+ b'+ %')6+ #11 ! # #1 04'6+ 04'+ ! 04'36+ electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 78/98 doc id 15081 rev 7 spi interface characteristics unless otherwise specified, the parameters given in ta bl e 5 0 are preliminary values derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in ta bl e 9 . refer to section 5.3.13: i/o current injection characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso). table 50. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode 12 mhz slave mode 12 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf 8 ns ducy(sck) spi slave input clock duty cycle slave mode 30 70 % t su(nss) (1) 1. preliminary values. nss setup time slave mode 4t pclk ns t h(nss) (1) nss hold time slave mode 2t pclk t w(sckh) (1) t w(sckl) (1) sck high and low time master mode, f pclk = 24 mhz, presc = 4 50 60 t su(mi) (1) t su(si) (1) data input setup time master mode 5 slave mode 5 t h(mi) (1) data input hold time master mode 5 t h(si) (1) slave mode 4 t a(so) (1)(2) 2. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. data output access time slave mode, f pclk = 24 mhz 0 3t pclk t dis(so) (1)(3) 3. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z data output disable time slave mode 2 10 t v(so) (1) data output valid time slave mode (after enable edge) 25 t v(mo) (1) data output valid time master mode (after enable edge) 5 t h(so) (1) data output hold time slave mode (after enable edge) 15 t h(mo) (1) master mode (after enable edge) 2 stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 79/98 figure 30. spi timing diagram - slave mode and cpha = 0 figure 31. spi timing diagram - slave mode and cpha = 1 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14134c sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 80/98 doc id 15081 rev 7 figure 32. spi timing diagram - master mode 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . hdmi consumer electronics control (cec) refer to section 5.3.13: i/o current injection characteristics for more details on the input/output alternate function characteristics. 5.3.18 12-bit adc characteristics unless otherwise specified, the parameters given in ta bl e 5 1 are preliminary values derived from tests performed under the ambient temperature, f pclk2 frequency and v dda supply voltage conditions summarized in ta bl e 9 . note: it is recommended to perform a calibration after each power-up. ai14136 sck output cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck output cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo) stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 81/98 equation 1: r ain max formula: the above formula ( equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). table 51. adc characteristics symbol parameter conditions min typ max unit v dda power supply 2.4 3.6 v v ref+ positive reference voltage 2.4 v dda v i vref current on the v ref input pin 160 (1) 220 (1) a f adc adc clock frequency 0.6 12 mhz f s (2) sampling rate 0.05 1 mhz f trig (2) external trigger frequency f adc = 12 mhz 823 khz 17 1/f adc v ain (3) conversion voltage range 0 (v ssa tied to ground) v ref+ v r ain (2) external input impedance see equation 1 and ta b l e 5 2 for details 50 k r adc (2) sampling switch resistance 1 k c adc (2) internal sample and hold capacitor 8pf t cal (2) calibration time f adc = 12 mhz 5.9 s 83 1/f adc t lat (2) injection trigger conversion latency f adc = 12 mhz 0.214 s 3 (4) 1/f adc t latr (2) regular trigger conversion latency f adc = 12 mhz 0.143 s 2 (4) 1/f adc t s (2) sampling time f adc = 12 mhz 0.125 17.1 s 1.5 239.5 1/f adc t stab (2) power-up time 0 0 1 s t conv (2) total conversion time (including sampling time) f adc = 12 mhz 1.17 21 s 14 to 252 (t s for sampling +12.5 for successive approximation) 1/f adc 1. preliminary values. 2. guaranteed by design, not tested in production. 3. v ref+ is internally connected to v dda 4. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 51 . r ain t s f adc c adc 2 n2 + () ln --------------------------------------------------------------- - r adc ? < electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 82/98 doc id 15081 rev 7 note: adc accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. table 52. r ain max for f adc = 12 mhz (1) 1. guaranteed by design, not tested in production. t s (cycles) t s (s) r ain max (k ) 1.5 0.125 0.4 7.5 0.625 5.9 13.5 1.125 11.4 28.5 2.375 25.2 41.5 3.45 37.2 55.5 4.625 50 71.5 5.96 na 239.5 20 na table 53. adc accuracy - limited test conditions (1)(2) 1. adc dc accuracy values are m easured after internal calibration. 2. preliminary values. symbol parameter test conditions typ max unit et total unadjusted error f pclk2 = 24 mhz, f adc = 12 mhz, r ain < 10 k , v dda = 3 v to 3.6 v v ref+ = v dda t a = 25 c measurements made after adc calibration 1.5 2.5 lsb eo offset error 1 2 eg gain error 0.5 1.5 ed differential linearity error 1.5 2 el integral linearity error 1.5 2 table 54. adc accuracy (1) (2) (3) 1. adc dc accuracy values are m easured after internal calibration. 2. better performance could be achieved in restricted v dd , frequency, v ref and temperature ranges. 3. preliminary values. symbol parameter test conditions typ max unit et total unadjusted error f pclk2 = 24 mhz, f adc = 12 mhz, r ain < 10 k , v dda = 2.4 v to 3.6 v t a = full operating range measurements made after adc calibration 2 5 lsb eo offset error 1.5 2.5 eg gain error 1.5 3 ed differential linearity error 1.5 2.5 el integral linearity error 1.5 4.5 stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 83/98 note: any positive inje ction current within th e limits specified for i inj(pin) and i inj(pin) in section 5.3.13 does not affect the adc accuracy. figure 33. adc accura cy characteristics figure 34. typical connection diagram using the adc 1. refer to table 51 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 35 or figure 36 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed them as close as possible to the chip. e o e g 1lsb ideal (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. 4095 4094 4093 5 4 3 2 1 0 7 6 1234567 4093 4094 4095 4096 (1) (2) e t e d e l (3) v dda v ssa ai14395b v ref+ 4096 (or depending on package)] v dda 4096 [1lsb ideal = ai14139d stm32f10xxx v dd ainx i l 1 a 0.6 v v t r ain (1) c parasitic v ain 0.6 v v t r adc (1) c adc (1) 12-bit converter sample and hold adc converter electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 84/98 doc id 15081 rev 7 figure 35. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ is available on 100-pin pa ckages and on tfbga64 packages. v ref- is available on 100-pin packages only. figure 36. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ and v ref- inputs are available only on 100-pin packages. v ref+ stm32f10xxx v dda v ssa /v ref- 1 f // 10 nf 1 f // 10 nf ai14380b v ref+ /v dda stm32f10xxx 1 f // 10 nf v ref? /v ssa ai14381b stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 85/98 5.3.19 dac elect rical specifications table 55. dac characteristics symbol parameter min typ max (1) unit comments v dda analog supply voltage 2.4 3.6 v v ref+ reference supply voltage 2.4 3.6 v v ref+ must always be below v dda v ssa ground 0 0 v r load (1) resistive load with buffer on 5 k r o (1) impedance output with buffer off 15 k when the buffer is off, the minimum resistive load between dac_out and v ss to have a 1% accuracy is 1.5 m c load (1) capacitive load 50 pf maximum capacitive load at dac_out pin (when the buffer is on). dac_out min (1) lower dac_out voltage with buffer on 0.2 v it gives the maximum output excursion of the dac. it corresponds to 12-bit input code (0x0e0) to (0xf1c) at v ref+ = 3.6 v and (0x155) and (0xeab) at v ref+ = 2.4 v dac_out max (1) higher dac_out voltage with buffer on v dda ? 0.2 v dac_out min (1) lower dac_out voltage with buffer off 0.5 mv it gives the maximum output excursion of the dac. dac_out max (1) higher dac_out voltage with buffer off v ref+ ? 1lsb v i ddvref+ dac dc current consumption in quiescent mode (standby mode) 220 a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs i dda dac dc current consumption in quiescent mode (2) 380 a with no load, middle code (0x800) on the inputs 480 a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs dnl (1) differential non linearity difference between two consecutive code-1lsb) 0.5 lsb given for the dac in 10-bit configuration 2 lsb given for the dac in 12-bit configuration inl (1) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023) 1 lsb given for the dac in 10-bit configuration 4 lsb given for the dac in 12-bit configuration electrical characteristics stm32f100xc, stm32f100xd, stm32f100xe 86/98 doc id 15081 rev 7 figure 37. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to r educe the output impedance and to dr ive external loads directly without the use of an external operational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. offset (1) offset error (difference between measured value at code (0x800) and the ideal value = v ref+ /2) 10 mv given for the dac in 12-bit configuration 3 lsb given for the dac in 10-bit at v ref+ = 3.6 v 12 lsb given for the dac in 12-bit at v ref+ = 3.6 v gain error (1) gain error 0.5 % given for the dac in 12-bit configuration t settling (1) settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when dac_out reaches final value 1lsb 34 sc load 50 pf, r load 5 k update rate (1) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) 1ms/sc load 50 pf, r load 5 k t wakeup (1) wakeup time from off state (setting the enx bit in the dac control register) 6.5 10 s c load 50 pf, r load 5 k input code between lowest and highest possible ones. psrr+ (1) power supply rejection ratio (to v dda ) (static dc measurement ?67 ?40 db no r load , c load = 50 pf 1. preliminary values. 2. quiescent mode refer to the state of the dac keeping steady value on the output, so no dynamic consumption is involved. table 55. dac characteristics (continued) symbol parameter min typ max (1) unit comments r load c load b u ffered/non- bu ffered dac dacx_out b u ffer(1) 12- b it digit a l to a n a log converter a i17157 stm32f100xc, stm32f100xd, stm32f100xe electrical characteristics doc id 15081 rev 7 87/98 5.3.20 temperature sen sor characteristics table 56. ts characteristics symbol parameter min typ max unit t l (1) v sense linearity with temperature 1 2 c avg_slope (1) average slope 4.0 4.3 4.6 mv/c v 25 (1) voltage at 25c 1.32 1.41 1.50 v t start (2) startup time 4 10 s t s_temp (3)(2) adc sampling time when reading the temperature 17.1 s 1. guaranteed by characterizati on, not tested in production. 2. guaranteed by design, not tested in production. 3. shortest sampling time can be determined in the application by multiple iterations. package characteristics stm32f100xc, stm32f100xd, stm32f100xe 88/98 doc id 15081 rev 7 6 package characteristics 6.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. stm32f100xc, stm32f100xd, stm32f100xe package characteristics doc id 15081 rev 7 89/98 1. drawing is not to scale. 2. dimensions are in millimeters. figure 38. lqfp144, 20 x 20 mm, 144-pin thin quad flat package outline figure 39. recommended footprint d1 d3 d e1 e3 e e pin 1 identification 73 72 37 36 109 144 108 1 aa2a1 b c a1 l l1 k seating plane c ccc c 0.25 mm gage plane me_1a 0.5 0.35 19.9 17.85 22.6 1.35 22.6 19.9 ai14 1 36 37 72 73 108 109 144 table 57. lqfp144, 20 x 20 mm, 144-pin thin quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a1.600.063 a1 0.05 0.15 0.002 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 21.80 22.00 22.20 0.8583 0.8661 0.874 d1 19.80 20.00 20.20 0.7795 0.7874 0.7953 d3 17.50 0.689 e 21.80 22.00 22.20 0.8583 0.8661 0.874 e1 19.80 20.00 20.20 0.7795 0.7874 0.7953 e3 17.50 0.689 e 0.50 0.0197 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 k 03.57 03.57 ccc 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm32f100xc, stm32f100xd, stm32f100xe 90/98 doc id 15081 rev 7 1. drawing is not to scale. 2. dimensions are in millimeters. figure 40. lqfp100 ? 14 x 14 mm, 100-pin low-profile quad flat package outline figure 41. recommended footprint d d1 d3 75 51 50 76 100 26 125 e3 e1 e e b pin 1 identification seating plane gage plane c a a2 a1 c ccc 0.25 mm 0.10 inch l l1 k c 1l_me 75 51 50 76 0.5 0. 3 16.7 14. 3 100 26 12. 3 25 1.2 16.7 1 a i14906 b table 58. lqpf100 ? 14 x 14 mm, 100-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 15.80 16.00 16.20 0.622 0.6299 0.6378 d1 13.80 14.00 14.20 0.5433 0.5512 0.5591 d3 12.00 0.4724 e 15.80 16.00 16.20 0.622 0.6299 0.6378 e1 13.80 14.00 14.20 0.5433 0.5512 0.5591 e3 12.00 0.4724 e 0.50 0.0197 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 k 03.57 03.57 ccc 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. stm32f100xc, stm32f100xd, stm32f100xe package characteristics doc id 15081 rev 7 91/98 1. drawing is not to scale. 2. dimensions are in millimeters. figure 42. lqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package outline figure 43. recommended footprint a a2 a1 c l1 l e e1 d d1 e b ai14398b 48 32 49 64 17 116 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909 table 59. lqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 12.00 0.4724 d1 10.00 0.3937 e 12.00 0.4724 e1 10.00 0.3937 e 0.50 0.0197 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 n number of pins 64 1. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm32f100xc, stm32f100xd, stm32f100xe 92/98 doc id 15081 rev 7 6.2 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 9: general operating conditions on page 37 . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: t a max is the maximum ambient temperature in c, ja is the package junction-to-ambient thermal resistance, in c/w, p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum powe r dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 6.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). ava ilable from www.jedec.org. table 60. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp 144 - 20 20 mm / 0.5 mm pitch 35 c/w thermal resistance junction-ambient lqfp 100 - 14 14 mm / 0.5 mm pitch 40 thermal resistance junction-ambient lqfp 64 - 10 10 mm / 0.5 mm pitch 49 stm32f100xc, stm32f100xd, stm32f100xe package characteristics doc id 15081 rev 7 93/98 6.2.2 selecting the pro duct temperature range when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in table 61: ordering information scheme . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. as applications do not commonly use the stm32f 100xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. the following examples show how to calculate the temperature range needed for a given application. example: high-performance application assuming the following application conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 8 i/os used at the same time in output mode at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 20 8 ma 0.4 v + 8 20 ma 1.3 v = 272 mw this gives: p intmax = 175 mw and p iomax = 272 mw p dmax = 175 + 272 = 447 mw thus: p dmax = 447 mw using the values obtained in ta b l e 6 0 t jmax is calculated as follows: ? for lqfp64, 49 c/w t jmax = 82 c + (49 c/w 447 mw) = 82 c + 20.1 c = 102.1 c this is within the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at least with the temperature range suffix 6 (see table 61: ordering information scheme ). example 2: high-temperature application using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature t j remains within the specified range. assuming the following application conditions: maximum ambient temperature t amax = 115 c (measured according to jesd51-2), i ddmax = 20 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 20 ma 3.5 v= 70 mw p iomax = 20 8 ma 0.4 v = 64 mw this gives: p intmax = 70 mw and p iomax = 64 mw: p dmax = 70 + 64 = 134 mw thus: p dmax = 134 mw package characteristics stm32f100xc, stm32f100xd, stm32f100xe 94/98 doc id 15081 rev 7 using the values obtained in ta b l e 6 0 t jmax is calculated as follows: ? for lqfp100, 40 c/w t jmax = 115 c + (40 c/w 134 mw) = 115 c + 5.4 c = 120.4 c this is within the range of the suffix 7 version parts (?40 < t j < 125 c). in this case, parts must be ordered at least with the temperature range suffix 7 (see table 61: ordering information scheme ). figure 44. lqfp100 p d max vs. t a 0 100 200 300 400 500 600 700 65 75 85 95 105 115 125 135 t a (c) p d (mw) suffix 6 suffix 7 stm32f100xc, stm32f100xd, stm32f100xe ordering information scheme doc id 15081 rev 7 95/98 7 ordering information scheme for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 61. ordering information scheme example: stm32 f 100 v c t 6 b xxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 100 = value line pin count r = 64 pins v = 100 pins z = 144 pins flash memory size c = 256 kbytes of flash memory d = 384 kbytes of flash memory e = 512 kbytes of flash memory package t = lqfp temperature range 6 = industrial temperature range, ?40 to 85 c 7 = industrial temperature range, ?40 to 105 c internal code b options xxx = programmed parts tr = tape and real revision history stm32f100xc, stm32f100xd, stm32f100xe 96/98 doc id 15081 rev 7 8 revision history table 62. document revision history date revision changes 09-oct-2008 1 initial release. 31-mar-2009 2 i/o information clarified on page 1. table 5: high-density stm32f100xx pin definitions modified. figure 5: memory map on page 26 modified. note modified in table 13: maximum current consumption in run mode, code with data processing running from flash and table 15: maximum current consumption in sleep mode, code running from flash or ram. table 20: high-speed external user clock characteristics and table 21: low-speed user external clock characteristics modified. acchsi max values modified in table 24: hsi oscillator characteristics. note modified in table 13: maximum current consumption in run mode, code with data processing running from flash and table 15: maximum current consumption in sleep mode, code running from flash or ram. figure 10, figure 11 and figure 12 show typical curves (titles changed). small text changes. 01-sep-2010 3 major revision of whole document. added lqfp144 package and additional peripherals (spi3, uart4, uart, tim5, 12, 14, 13, fsmc). 18-oct-2010 4 updated power consumption data in ta bl e 1 3 to ta bl e 1 6 updated section 5.3.11: emc characteristics on page 66 11-apr-2011 5 added section 2.2.6: lcd parallel interface on page 13 in table 4 on page 24 moved tim15_bkin and tim17_bkin from remap to default column. updated description of pa3, pa5 and pf6 to pf10. updated footnotes below table 6: voltage characteristics on page 36 and table 7: current characteristics on page 37 added vbat values in table 16: typical and maximum current consumptions in stop and standby modes on page 43 updated tw min in table 20: high-speed external user clock characteristics on page 47 updated startup time in table 23: lse oscillator characteristics (flse = 32.768 khz) on page 51 added hsi clock accuracy values in table 24: hsi oscillator characteristics on page 52 updated fsmc synchronous waveforms and timings on page 60 updated table 43: i/o static characteristics on page 69 added section 5.3.13: i/o current injection characteristics on page 68 corrected ttl and cmos designations in table 44: output voltage characteristics on page 72 stm32f100xc, stm32f100xd, stm32f100xe revision history doc id 15081 rev 7 97/98 08-jun-2012 6 updated table 7: current characteristics on page 37 corrected ?clkl-noel? in section 5.3.10: fsmc characteristics on page 54 updated table 48: i2c characteristics on page 76 corrected note ?n on-robust ? in section 5.3.18: 12-bit adc characteristics on page 80 updated figure 1: stm32f100xx value line block diagram on page 11 updated section 5.3.14: i/o port characteristics on page 69 updated section 2.2.22: gpios (general -purpose inputs/outputs) on page 20 updated table 4: high-density stm32f100xx pin definitions on page 24 updated section 5.3.1: general operating conditions on page 37 updated pd0 and pd1 in table 4: high-density stm32f100xx pin definitions on page 24 17-sep-2012 7 updated p d max specifications in table 9: general operating conditions added footnote to idda parameter description in table 55: dac characteristics table 62. document revision history (continued) date revision changes stm32f100xc, stm32f100xd, stm32f100xe 98/98 doc id 15081 rev 7 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
Price & Availability of STM32F100VCT6
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |